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Date: Fri, 24 Mar 2017 10:22:49 +0800
From: Elaine Zhang <zhangqing@...k-chips.com>
To: Lee Jones <lee.jones@...aro.org>
CC: lgirdwood@...il.com, broonie@...nel.org, huangtao@...k-chips.com,
xxx@...k-chips.com, linux-rockchip@...ts.infradead.org,
linux-kernel@...r.kernel.org, chenjh@...k-chips.com,
robh+dt@...nel.org, mark.rutland@....com,
devicetree@...r.kernel.org, w.egorov@...tec.de
Subject: Re: [PATCH v4 2/7] mfd: rk808: add rk805 regs addr and ID
On 03/23/2017 08:15 PM, Lee Jones wrote:
> On Fri, 17 Mar 2017, Elaine Zhang wrote:
>
>> Signed-off-by: Elaine Zhang <zhangqing@...k-chips.com>
>> ---
>> include/linux/mfd/rk808.h | 119 ++++++++++++++++++++++++++++++++++++++++++++++
>> 1 file changed, 119 insertions(+)
>>
>> diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h
>> index 54feb140c210..a133309b52f9 100644
>> --- a/include/linux/mfd/rk808.h
>> +++ b/include/linux/mfd/rk808.h
>> @@ -206,6 +206,96 @@ enum rk818_reg {
>> #define RK818_USB_ILMIN_2000MA 0x7
>> #define RK818_USB_CHG_SD_VSEL_MASK 0x70
>>
>> +/* RK805 */
>> +enum rk805_reg {
>> + RK805_ID_DCDC1,
>> + RK805_ID_DCDC2,
>> + RK805_ID_DCDC3,
>> + RK805_ID_DCDC4,
>> + RK805_ID_LDO1,
>> + RK805_ID_LDO2,
>> + RK805_ID_LDO3,
>> +};
>> +
>> +/* INTERRUPT REGISTER */
>> +#define RK805_INT_STS_REG 0x4C
>> +#define RK805_INT_STS_MSK_REG 0x4D
>> +#define RK805_GPIO_IO_POL_REG 0x50
>> +#define RK805_OUT_REG 0x52
>> +#define RK805_ON_SOURCE_REG 0xAE
>> +#define RK805_OFF_SOURCE_REG 0xAF
>> +
>> +/* POWER CHANNELS ENABLE REGISTER */
>> +#define RK805_DCDC_EN_REG 0x23
>> +#define RK805_SLP_DCDC_EN_REG 0x25
>> +#define RK805_SLP_LDO_EN_REG 0x26
>> +#define RK805_LDO_EN_REG 0x27
>> +
>> +/* CONFIG REGISTER */
>> +#define RK805_THERMAL_REG 0x22
>> +
>> +/* BUCK AND LDO CONFIG REGISTER */
>> +#define RK805_BUCK_LDO_SLP_LP_EN_REG 0x2A
>> +#define RK805_BUCK1_CONFIG_REG 0x2E
>> +#define RK805_BUCK1_ON_VSEL_REG 0x2F
>> +#define RK805_BUCK1_SLP_VSEL_REG 0x30
>> +#define RK805_BUCK2_CONFIG_REG 0x32
>> +#define RK805_BUCK2_ON_VSEL_REG 0x33
>> +#define RK805_BUCK2_SLP_VSEL_REG 0x34
>> +#define RK805_BUCK3_CONFIG_REG 0x36
>> +#define RK805_BUCK4_CONFIG_REG 0x37
>> +#define RK805_BUCK4_ON_VSEL_REG 0x38
>> +#define RK805_BUCK4_SLP_VSEL_REG 0x39
>> +#define RK805_LDO1_ON_VSEL_REG 0x3B
>> +#define RK805_LDO1_SLP_VSEL_REG 0x3C
>> +#define RK805_LDO2_ON_VSEL_REG 0x3D
>> +#define RK805_LDO2_SLP_VSEL_REG 0x3E
>> +#define RK805_LDO3_ON_VSEL_REG 0x3F
>> +#define RK805_LDO3_SLP_VSEL_REG 0x40
>> +#define RK805_OUT_REG 0x52
>> +#define RK805_ON_SOURCE_REG 0xAE
>> +#define RK805_OFF_SOURCE_REG 0xAF
>
> Why aren't all of these in numerical order?
I will fixed it in patch V5.
>
>> +#define RK805_NUM_REGULATORS 7
>> +
>> +#define RK805_PWRON_FALL_RISE_INT_EN 0x0
>> +#define RK805_PWRON_FALL_RISE_INT_MSK 0x81
>> +
>> +/* RK805 IRQ Definitions */
>> +#define RK805_IRQ_PWRON_RISE 0
>> +#define RK805_IRQ_VB_LOW 1
>> +#define RK805_IRQ_PWRON 2
>> +#define RK805_IRQ_PWRON_LP 3
>> +#define RK805_IRQ_HOTDIE 4
>> +#define RK805_IRQ_RTC_ALARM 5
>> +#define RK805_IRQ_RTC_PERIOD 6
>> +#define RK805_IRQ_PWRON_FALL 7
>> +
>> +#define RK805_IRQ_PWRON_RISE_MSK BIT(0)
>> +#define RK805_IRQ_VB_LOW_MSK BIT(1)
>> +#define RK805_IRQ_PWRON_MSK BIT(2)
>> +#define RK805_IRQ_PWRON_LP_MSK BIT(3)
>> +#define RK805_IRQ_HOTDIE_MSK BIT(4)
>> +#define RK805_IRQ_RTC_ALARM_MSK BIT(5)
>> +#define RK805_IRQ_RTC_PERIOD_MSK BIT(6)
>> +#define RK805_IRQ_PWRON_FALL_MSK BIT(7)
>> +
>> +#define RK805_PWR_RISE_INT_STATUS BIT(0)
>> +#define RK805_VB_LOW_INT_STATUS BIT(1)
>> +#define RK805_PWRON_INT_STATUS BIT(2)
>> +#define RK805_PWRON_LP_INT_STATUS BIT(3)
>> +#define RK805_HOTDIE_INT_STATUS BIT(4)
>> +#define RK805_ALARM_INT_STATUS BIT(5)
>> +#define RK805_PERIOD_INT_STATUS BIT(6)
>> +#define RK805_PWR_FALL_INT_STATUS BIT(7)
>> +
>> +#define RK805_BUCK1_2_ILMAX_MASK (3 << 6)
>> +#define RK805_BUCK3_4_ILMAX_MASK (3 << 3)
>> +#define RK805_RTC_PERIOD_INT_MASK (1 << 6)
>> +#define RK805_RTC_ALARM_INT_MASK (1 << 5)
>> +#define RK805_INT_ALARM_EN (1 << 3)
>> +#define RK805_INT_TIMER_EN (1 << 2)
>> +
>> /* RK808 IRQ Definitions */
>> #define RK808_IRQ_VOUT_LO 0
>> #define RK808_IRQ_VB_LO 1
>> @@ -298,7 +388,14 @@ enum rk818_reg {
>> #define VOUT_LO_INT BIT(0)
>> #define CLK32KOUT2_EN BIT(0)
>>
>> +#define TEMP115C 0x0c
>> +#define TEMP_HOTDIE_MSK 0x0c
>> +#define SLP_SD_MSK (0x3 << 2)
>> +#define SHUTDOWN_FUN (0x2 << 2)
>> +#define SLEEP_FUN (0x1 << 2)
>> #define RK8XX_ID_MSK 0xfff0
>> +#define FPWM_MODE BIT(7)
>> +
>> enum {
>> BUCK_ILMIN_50MA,
>> BUCK_ILMIN_100MA,
>> @@ -322,6 +419,28 @@ enum {
>> };
>>
>> enum {
>> + RK805_BUCK1_2_ILMAX_2500MA,
>> + RK805_BUCK1_2_ILMAX_3000MA,
>> + RK805_BUCK1_2_ILMAX_3500MA,
>> + RK805_BUCK1_2_ILMAX_4000MA,
>> +};
>> +
>> +enum {
>> + RK805_BUCK3_ILMAX_1500MA,
>> + RK805_BUCK3_ILMAX_2000MA,
>> + RK805_BUCK3_ILMAX_2500MA,
>> + RK805_BUCK3_ILMAX_3000MA,
>> +};
>> +
>> +enum {
>> + RK805_BUCK4_ILMAX_2000MA,
>> + RK805_BUCK4_ILMAX_2500MA,
>> + RK805_BUCK4_ILMAX_3000MA,
>> + RK805_BUCK4_ILMAX_3500MA,
>> +};
>> +
>> +enum {
>> + RK805_ID = 0x8050,
>> RK808_ID = 0x0000,
>> RK818_ID = 0x8181,
>> };
>
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