lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-Id: <20170329002929.54e022d61751a84221a4635e@kernel.org>
Date:   Wed, 29 Mar 2017 00:29:29 +0900
From:   Masami Hiramatsu <mhiramat@...nel.org>
To:     Ravi Bangoria <ravi.bangoria@...ux.vnet.ibm.com>
Cc:     acme@...hat.com, alexis.berlemont@...il.com,
        linux-kernel@...r.kernel.org, peterz@...radead.org,
        mingo@...hat.com, alexander.shishkin@...ux.intel.com,
        naveen.n.rao@...ux.vnet.ibm.com, mpe@...erman.id.au,
        hemant@...ux.vnet.ibm.com
Subject: Re: [PATCH v3 0/3] perf/sdt: Hardening argument support

Hi Arnaldo,

please pull this, I've already acked to this series.

Thank you, 

On Tue, 28 Mar 2017 15:17:51 +0530
Ravi Bangoria <ravi.bangoria@...ux.vnet.ibm.com> wrote:

> SDT event argument support on x86 is recently added to Perf. But
> there are couple of issues with it.
> 
> It lacks renaming mapping for few 8 bit registers: al, bl, cl, dl,
> ah, bh, ch and dh. SDT events using these registers in arguments
> are failing at 'perf probe'. Add renaming logic to them. (patch 1)
> 
> It still has x86 specific code in general code. It also fails to
> convert arguments having no offset but still surrounds register with
> parenthesis for ex. 8@(%rdi) is converted to +(%di):u64, which is
> rejected by uprobe_events. Also, 'perf probe' is failing for *all SDT
> events on all archs except x86*. Solve these issues. (patch 2)
> 
> Add argument parser for powerpc. (patch 3)
> 
> Changes in v3:
>   - (patch 1) Add renaming entries for ah, bh, ch and dh registers.[1]
> 
>   - (patch 1) v2 contains silly copy-paste error. It maps all al, bl...
>     registers to ax. Fix that.
> 
>   - (patch 2) Fix typo 'constant'.
> 
>   - Patch 2 is not applying cleanly on top of patch 1 after adding
>     ah, bh... registers. Fix that.
> 
> v2: https://lkml.org/lkml/2017/3/27/118
> 
> This patch is prepared on top of acme/perf/core.
> 
> [1] https://lkml.org/lkml/2017/3/27/462
> 
> Ravi Bangoria (3):
>   perf/sdt/x86: Add renaming logic for (missing) 8 bit registers
>   perf/sdt/x86: Move OP parser to tools/perf/arch/x86/
>   perf/sdt/powerpc: Add argument support
> 
>  tools/perf/arch/powerpc/util/perf_regs.c | 111 ++++++++++++++++++
>  tools/perf/arch/x86/util/perf_regs.c     | 187 +++++++++++++++++++++++++------
>  tools/perf/util/perf_regs.c              |   6 +-
>  tools/perf/util/perf_regs.h              |  11 +-
>  tools/perf/util/probe-file.c             | 132 +++++++---------------
>  5 files changed, 313 insertions(+), 134 deletions(-)
> 
> -- 
> 2.9.3
> 


-- 
Masami Hiramatsu <mhiramat@...nel.org>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ