linux-kernel - [RFC PATCH 2/6] x86/apic: Construct a framework for setuping APIC mode as soon as possible

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Date:   Wed, 29 Mar 2017 22:55:29 +0800
From:   Dou Liyang <douly.fnst@...fujitsu.com>
To:     <x86@...nel.org>, <linux-kernel@...r.kernel.org>
CC:     <tglx@...utronix.de>, <mingo@...nel.org>, <ebiederm@...ssion.com>,
        <bhe@...hat.com>, <hpa@...or.com>, <izumi.taku@...fujitsu.com>,
        Dou Liyang <douly.fnst@...fujitsu.com>
Subject: [RFC PATCH 2/6] x86/apic: Construct a framework for setuping APIC mode as soon as possible

Now, there are two ways to setup local apic and io-apic in X86 arch:
  1. In an SMP-capable system, it will be done when preparing the
cpus in native_smp_prepare_boot_cpu().
  2. If UP_LATE_INIT is y, it will be done in smp_init()

And, there are many switches in kernel which can determine the way of
APIC mode setup, as shown below:

  1. kconfig :
     CONFIG_X86_64; CONFIG_X86_LOCAL_APIC; CONFIG_x86_IO_APIC
  2. kernel option: disable_apic; skip_ioapic_setup
  3. BIOS : boot_cpu_has(X86_FEATURE_APIC)
  4. MP table: smp_found_config
  5. ACPI: acpi_lapic; acpi_ioapic; nr_ioapic

The setup is late which cause the dump-capture kernel hangs with 'notsc'
option in 1st kernel option. and the use of these switches is messily.

Before make the APIC mode setup earlier, construct a framework first to
prepare for the work and make the logic clear.

Signed-off-by: Dou Liyang <douly.fnst@...fujitsu.com>
---
 arch/x86/include/asm/apic.h |  2 ++
 arch/x86/kernel/apic/apic.c | 73 +++++++++++++++++++++++++++++++++++++++++++++
 arch/x86/kernel/irqinit.c   |  3 ++
 3 files changed, 78 insertions(+)

diff --git a/arch/x86/include/asm/apic.h b/arch/x86/include/asm/apic.h
index 20ac73c..c973f18 100644
--- a/arch/x86/include/asm/apic.h
+++ b/arch/x86/include/asm/apic.h
@@ -172,6 +172,8 @@ static inline void disable_local_APIC(void) { }
 # define setup_secondary_APIC_clock x86_init_noop
 static inline void lapic_update_tsc_freq(void) { }
 static inline void apic_virture_wire_mode_setup(void) {}
+static inline void init_bsp_APIC(void) {}
+
 #endif /* !CONFIG_X86_LOCAL_APIC */
 
 #ifdef CONFIG_X86_X2APIC
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index f4fc949..bf4ccd0 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1153,6 +1153,63 @@ void __init sync_Arb_IDs(void)
 			APIC_INT_LEVELTRIG | APIC_DM_INIT);
 }
 
+enum apic_bsp_mode {
+	APIC_BSP_MODEL_PIC = 0,
+	APIC_BSP_MODEL_VIRTUAL_WIRE,
+	APIC_BSP_MODEL_SYMMETRIC_IO,
+	APIC_BSP_MODEL_COUNT
+};
+
+static int __init apic_bsp_mode_check(void)
+{
+
+	/* Check kernel option */
+	if (disable_apic) {
+		pr_info("APIC disabled by kernel option\n");
+		return APIC_BSP_MODEL_PIC;
+	}
+	/* Check BOIS */
+#ifdef CONFIG_X86_64
+	/* On 64-bit, The APIC is integrated, So, must have APIC feature */
+	if (!boot_cpu_has(X86_FEATURE_APIC)) {
+		disable_apic = 1;
+		pr_info("Apic disabled by BIOS\n");
+		return APIC_BSP_MODEL_PIC;
+	}
+#else
+	if (!boot_cpu_has(X86_FEATURE_APIC) &&
+		APIC_INTEGRATED(boot_cpu_apic_version)) {
+		pr_err("BIOS bug, local APIC #%d not detected!...\n",
+			boot_cpu_physical_apicid);
+		pr_err("... forcing use of dummy APIC emulation (tell your hw vendor)\n");
+		return APIC_BSP_MODEL_PIC;
+	}
+#endif
+	/*
+	 * Check MP table, if neither an integrated nor a separate chip
+	 * doesn't exist.
+	 */
+	if (!boot_cpu_has(X86_FEATURE_APIC) && !smp_found_config) {
+		pr_info("BOIS don't support APIC, and no SMP configuration.\n");
+		return APIC_BSP_MODEL_PIC;
+	}
+
+	/* Check MP table, ps: if the virtual wire has been setup */
+	if (!smp_found_config) {
+		disable_ioapic_support();
+
+		/* Check local APIC, if SMP_NO_CONFIG */
+		if (!acpi_lapic)
+			pr_info("SMP motherboard not detected\n");
+
+		return APIC_BSP_MODEL_VIRTUAL_WIRE;
+	}
+
+	/* Other checks of ACPI options will be done in each setup function */
+
+	return APIC_BSP_MODEL_SYMMETRIC_IO;
+}
+
 /*
  * Setup the through-local-APIC virtual wire mode.
  */
@@ -1202,6 +1259,22 @@ void apic_virture_wire_mode_setup(void)
 	apic_write(APIC_LVT1, value);
 }
 
+/* init the interrupt routing model for the BSP */
+void __init init_bsp_APIC(void)
+{
+	switch (apic_bsp_mode_check()) {
+	case APIC_BSP_MODEL_PIC:
+		pr_info("Keep in PIC mode(8259)\n");
+		return;
+	case APIC_BSP_MODEL_VIRTUAL_WIRE:
+		pr_info("switch to virtual wire model.\n");
+		return;
+	case APIC_BSP_MODEL_SYMMETRIC_IO:
+		pr_info("switch to symmectic I/O model.\n");
+		return;
+	}
+}
+
 static void lapic_setup_esr(void)
 {
 	unsigned int oldvalue, value, maxlvt;
diff --git a/arch/x86/kernel/irqinit.c b/arch/x86/kernel/irqinit.c
index b6ef4ea..f30fb16 100644
--- a/arch/x86/kernel/irqinit.c
+++ b/arch/x86/kernel/irqinit.c
@@ -197,4 +197,7 @@ void __init native_init_IRQ(void)
 #ifdef CONFIG_X86_32
 	irq_ctx_init(smp_processor_id());
 #endif
+
+	/* init the IRQ Mode for BSP */
+	init_bsp_APIC();
 }
-- 
2.5.5