[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <1490862222-723-2-git-send-email-guochun.mao@mediatek.com>
Date: Thu, 30 Mar 2017 16:23:42 +0800
From: Guochun Mao <guochun.mao@...iatek.com>
To: Boris Brezillon <boris.brezillon@...e-electrons.com>,
Marek Vasut <marek.vasut@...il.com>
CC: David Woodhouse <dwmw2@...radead.org>,
Richard Weinberger <richard@....at>,
Cyrille Pitchen <cyrille.pitchen@...el.com>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Matthias Brugger <matthias.bgg@...il.com>,
Russell King <linux@...linux.org.uk>,
<linux-mtd@...ts.infradead.org>, <devicetree@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-mediatek@...ts.infradead.org>,
<linux-kernel@...r.kernel.org>,
Guochun Mao <guochun.mao@...iatek.com>
Subject: [PATCH V1 1/1] mtd: mtk-nor: set controller to 4B mode with large capacity flash
when nor's size larger than 16MByte, nor and controller should
enter 4Byte mode simultaneously.
Signed-off-by: Guochun Mao <guochun.mao@...iatek.com>
---
drivers/mtd/spi-nor/mtk-quadspi.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/drivers/mtd/spi-nor/mtk-quadspi.c b/drivers/mtd/spi-nor/mtk-quadspi.c
index e661877..05cd8a8 100644
--- a/drivers/mtd/spi-nor/mtk-quadspi.c
+++ b/drivers/mtd/spi-nor/mtk-quadspi.c
@@ -369,6 +369,13 @@ static int mt8173_nor_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf,
/* We only handle 1 byte */
ret = mt8173_nor_wr_sr(mt8173_nor, *buf);
break;
+ case SPINOR_OP_EN4B:
+ /* Set nor controller to 4-byte address mode,
+ * and simultaneously set nor flash.
+ * This case should cooperate with default operation.
+ */
+ writeb(readb(mt8173_nor->base + MTK_NOR_DUAL_REG) | 0x10,
+ mt8173_nor->base + MTK_NOR_DUAL_REG);
default:
ret = mt8173_nor_do_tx_rx(mt8173_nor, opcode, buf, len, NULL, 0);
if (ret)
--
1.7.9.5
Powered by blists - more mailing lists