linux-kernel - [tip:perf/core] x86/events/amd/iommu: Clean up perf_iommu

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Message-ID: <tip-dc6ca5e47d44c11a111807208595ff6a8fcd2a83@git.kernel.org>
Date:   Thu, 30 Mar 2017 01:35:20 -0700
From:   tip-bot for Suravee Suthikulpanit <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     bp@...e.de, jolsa@...hat.com, tglx@...utronix.de,
        torvalds@...ux-foundation.org, vincent.weaver@...ne.edu,
        alexander.shishkin@...ux.intel.com, mingo@...nel.org,
        eranian@...gle.com, joro@...tes.org, peterz@...radead.org,
        linux-kernel@...r.kernel.org, acme@...hat.com, hpa@...or.com,
        suravee.suthikulpanit@....com, Suravee.Suthikulpanit@....com
Subject: [tip:perf/core] x86/events/amd/iommu: Clean up perf_iommu_read()

Commit-ID:  dc6ca5e47d44c11a111807208595ff6a8fcd2a83
Gitweb:     http://git.kernel.org/tip/dc6ca5e47d44c11a111807208595ff6a8fcd2a83
Author:     Suravee Suthikulpanit <Suravee.Suthikulpanit@....com>
AuthorDate: Fri, 24 Feb 2017 02:48:15 -0600
Committer:  Ingo Molnar <mingo@...nel.org>
CommitDate: Thu, 30 Mar 2017 09:53:52 +0200

x86/events/amd/iommu: Clean up perf_iommu_read()

Fix coding style and use GENMASK_ULL().

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@....com>
Signed-off-by: Borislav Petkov <bp@...e.de>
Signed-off-by: Peter Zijlstra (Intel) <peterz@...radead.org>
Cc: Alexander Shishkin <alexander.shishkin@...ux.intel.com>
Cc: Arnaldo Carvalho de Melo <acme@...hat.com>
Cc: Jiri Olsa <jolsa@...hat.com>
Cc: Jörg Rödel <joro@...tes.org>
Cc: Linus Torvalds <torvalds@...ux-foundation.org>
Cc: Peter Zijlstra <peterz@...radead.org>
Cc: Stephane Eranian <eranian@...gle.com>
Cc: Thomas Gleixner <tglx@...utronix.de>
Cc: Vince Weaver <vincent.weaver@...ne.edu>
Cc: iommu@...ts.linux-foundation.org
Link: http://lkml.kernel.org/r/1487926102-13073-4-git-send-email-Suravee.Suthikulpanit@amd.com
Signed-off-by: Ingo Molnar <mingo@...nel.org>
---
 arch/x86/events/amd/iommu.c | 16 ++++++----------
 1 file changed, 6 insertions(+), 10 deletions(-)

diff --git a/arch/x86/events/amd/iommu.c b/arch/x86/events/amd/iommu.c
index e112f49..d4375da 100644
--- a/arch/x86/events/amd/iommu.c
+++ b/arch/x86/events/amd/iommu.c
@@ -320,9 +320,7 @@ static void perf_iommu_start(struct perf_event *event, int flags)
 
 static void perf_iommu_read(struct perf_event *event)
 {
-	u64 count = 0ULL;
-	u64 prev_raw_count = 0ULL;
-	u64 delta = 0ULL;
+	u64 count, prev, delta;
 	struct hw_perf_event *hwc = &event->hw;
 
 	amd_iommu_pc_get_set_reg_val(_GET_DEVID(event),
@@ -330,18 +328,16 @@ static void perf_iommu_read(struct perf_event *event)
 				IOMMU_PC_COUNTER_REG, &count, false);
 
 	/* IOMMU pc counter register is only 48 bits */
-	count &= 0xFFFFFFFFFFFFULL;
+	count &= GENMASK_ULL(47, 0);
 
-	prev_raw_count =  local64_read(&hwc->prev_count);
-	if (local64_cmpxchg(&hwc->prev_count, prev_raw_count,
-					count) != prev_raw_count)
+	prev = local64_read(&hwc->prev_count);
+	if (local64_cmpxchg(&hwc->prev_count, prev, count) != prev)
 		return;
 
-	/* Handling 48-bit counter overflowing */
-	delta = (count << COUNTER_SHIFT) - (prev_raw_count << COUNTER_SHIFT);
+	/* Handle 48-bit counter overflow */
+	delta = (count << COUNTER_SHIFT) - (prev << COUNTER_SHIFT);
 	delta >>= COUNTER_SHIFT;
 	local64_add(delta, &event->count);
-
 }
 
 static void perf_iommu_stop(struct perf_event *event, int flags)