linux-kernel - Re: [PATCH] mmc: sdhci-of-at91: fix MMC_DDR

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Message-ID: <CAPDyKFraFT-ML8uU-3xQNQGKUs-SaVi=wg6ULepRxTPUGRFxqA@mail.gmail.com>
Date:   Thu, 30 Mar 2017 21:30:30 +0200
From:   Ulf Hansson <ulf.hansson@...aro.org>
To:     Ludovic Desroches <ludovic.desroches@...rochip.com>
Cc:     Adrian Hunter <adrian.hunter@...el.com>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        nicolas.ferre@...rochip.com, "# 4 . 4+" <stable@...r.kernel.org>
Subject: Re: [PATCH] mmc: sdhci-of-at91: fix MMC_DDR_52 timing selection

On 28 March 2017 at 11:00, Ludovic Desroches
<ludovic.desroches@...rochip.com> wrote:
> The controller has different timings for MMC_TIMING_UHS_DDR50 and
> MMC_TIMING_MMC_DDR52. Configuring the controller with SDHCI_CTRL_UHS_DDR50,
> when MMC_TIMING_MMC_DDR52 timings are requested, is not correct and can
> lead to unexpected behavior.
>
> Signed-off-by: Ludovic Desroches <ludovic.desroches@...rochip.com>
> Fixes: bb5f8ea4d514 ("mmc: sdhci-of-at91: introduce driver for the Atmel SDMMC")
> Cc: <stable@...r.kernel.org> # 4.4+

Thanks, applied for fixes!

And thanks for really getting to bottom to fix this issue properly!

Kind regards
Uffe

> ---
>
> Hi,
>
> Here is the proper fix (I hope!) to the issue I have since commit e173f8911f09
> ("mmc: core: Update CMD13 polling policy when switch to HS DDR mode"). This
> commit was probably not the root cause but causes some side effect due to a
> bad timing configuration.
>
> I can't explain how it was working before but for sure I was not configuring
> properly the controller timings.
>
> Regards
>
>
>  drivers/mmc/host/sdhci-of-at91.c | 11 ++++++++++-
>  1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-of-at91.c b/drivers/mmc/host/sdhci-of-at91.c
> index 814571f..7611fd6 100644
> --- a/drivers/mmc/host/sdhci-of-at91.c
> +++ b/drivers/mmc/host/sdhci-of-at91.c
> @@ -29,6 +29,8 @@
>
>  #include "sdhci-pltfm.h"
>
> +#define SDMMC_MC1R     0x204
> +#define                SDMMC_MC1R_DDR          BIT(3)
>  #define SDMMC_CACR     0x230
>  #define                SDMMC_CACR_CAPWREN      BIT(0)
>  #define                SDMMC_CACR_KEY          (0x46 << 8)
> @@ -101,11 +103,18 @@ static void sdhci_at91_set_power(struct sdhci_host *host, unsigned char mode,
>         sdhci_set_power_noreg(host, mode, vdd);
>  }
>
> +void sdhci_at91_set_uhs_signaling(struct sdhci_host *host, unsigned int timing)
> +{
> +       if (timing == MMC_TIMING_MMC_DDR52)
> +               sdhci_writeb(host, SDMMC_MC1R_DDR, SDMMC_MC1R);
> +       sdhci_set_uhs_signaling(host, timing);
> +}
> +
>  static const struct sdhci_ops sdhci_at91_sama5d2_ops = {
>         .set_clock              = sdhci_at91_set_clock,
>         .set_bus_width          = sdhci_set_bus_width,
>         .reset                  = sdhci_reset,
> -       .set_uhs_signaling      = sdhci_set_uhs_signaling,
> +       .set_uhs_signaling      = sdhci_at91_set_uhs_signaling,
>         .set_power              = sdhci_at91_set_power,
>  };
>
> --
> 2.9.0
>