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Date:   Sun, 2 Apr 2017 16:58:44 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>
Cc:     Andy Shevchenko <andy@...radead.org>,
        Zha Qipeng <qipeng.zha@...el.com>,
        "dvhart@...radead.org" <dvhart@...radead.org>,
        Guenter Roeck <linux@...ck-us.net>,
        Wim Van Sebroeck <wim@...ana.be>, sathyaosid@...il.com,
        David Box <david.e.box@...ux.intel.com>,
        Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com>,
        Platform Driver <platform-driver-x86@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-watchdog@...r.kernel.org
Subject: Re: [PATCH v4 2/5] platform/x86: intel_pmc_ipc: Add pmc gcr
 read/write/update api's

On Sat, Apr 1, 2017 at 2:27 AM, Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@...ux.intel.com> wrote:
> This patch adds API's to read/write/update PMC GC registers.
> PMC dependent devices like iTCO_WDT, Telemetry has requirement

iTCO_wdt

> to acces GCR registers. These API's can be used for this
> purpose.

> --- a/drivers/platform/x86/intel_pmc_ipc.c
> +++ b/drivers/platform/x86/intel_pmc_ipc.c

> +static inline int is_gcr_valid(u32 offset)

Pointer to ipcdev should be a parameter to this function.

> +{
> +       if (!ipcdev.has_gcr_regs)
> +               return -EACCES;
> +
> +       if (offset > PLAT_RESOURCE_GCR_SIZE)
> +               return -EINVAL;
> +
> +       return 0;
> +}

> +/**
> + * intel_pmc_gcr_update() - Update PMC GCR register bits
> + * @offset:    offset of GCR register from GCR address base
> + * @mask:      bit mask for update operation
> + * @val:       update value
> + *

> + * Updates the bits of given GCR register as specified by
> + * mask and val

-> * @mask and @val.

You would need to refresh how to use kernel doc.

> + *
> + * Return:     negative value on error or 0 on success.
> + */

With Best Regards,
Andy Shevchenko

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