linux-kernel - Re: [PATCH v5 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr read/write/update api's

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Date:   Tue, 4 Apr 2017 16:53:57 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Kuppuswamy Sathyanarayanan 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>
Cc:     Andy Shevchenko <andy@...radead.org>,
        Zha Qipeng <qipeng.zha@...el.com>,
        "dvhart@...radead.org" <dvhart@...radead.org>,
        Guenter Roeck <linux@...ck-us.net>,
        Wim Van Sebroeck <wim@...ana.be>,
        Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@...il.com>,
        David Box <david.e.box@...ux.intel.com>,
        Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com>,
        Platform Driver <platform-driver-x86@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-watchdog@...r.kernel.org
Subject: Re: [PATCH v5 2/6] platform/x86: intel_pmc_ipc: Add pmc gcr
 read/write/update api's

On Tue, Apr 4, 2017 at 3:24 AM, Kuppuswamy Sathyanarayanan
<sathyanarayanan.kuppuswamy@...ux.intel.com> wrote:
> This patch adds API's to read/write/update PMC GC registers.
> PMC dependent devices like iTCO_wdt, Telemetry has requirement
> to acces GCR registers. These API's can be used for this
> purpose.

> +/* GCR reg offsets from gcr base*/
> +#define PMC_GCR_PMC_CFG_REG            0x08
> +

> --- a/drivers/platform/x86/intel_pmc_ipc.c
> +++ b/drivers/platform/x86/intel_pmc_ipc.c
> @@ -127,6 +127,7 @@ static struct intel_pmc_ipc_dev {
>
>         /* gcr */
>         resource_size_t gcr_base;

> +       void __iomem *gcr_mem_base;
>         int gcr_size;

Rearrange those lines to make __iomem pointer latter.

> +static inline int is_gcr_valid(u32 offset)

Same comment as previously. It should take a pointer to struct
intel_pmc_ipc_dev as a parameter.

> +/**
> + * intel_pmc_gcr_write() - Write PMC GCR register
> + * @offset:    offset of GCR register from GCR address base
> + * @data:      register update value
> + *
> + * Writes the PMC GCR register of given offset with given
> + * value

You have to use proper punctuation in the sentences in full Description section.

> +/**
> + * intel_pmc_gcr_update() - Update PMC GCR register bits
> + * @offset:    offset of GCR register from GCR address base
> + * @mask:      bit mask for update operation
> + * @val:       update value
> + *
> + * Updates the bits of given GCR register as specified by
> + * @mask and @val

Ditto.

> +int intel_pmc_gcr_update(u32 offset, u32 mask, u32 val)
> +{

> +       u32 orig, tmp;

One of them is redundant.

I would go just with
u32 value;

> +       writel(tmp, ipcdev.gcr_mem_base + offset);
> +
> +       tmp = readl(ipcdev.gcr_mem_base + offset);

> +

Redundant.

> +       if ((tmp & mask) != (val & mask)) {

Why?! It the a case when writel() will fail? Needs to be commented.

> +               ret = -EIO;
> +               goto gcr_update_err;
> +       }
> +

> +gcr_update_err:

The keyword  'unlock' is missed in the label name.

> +       mutex_unlock(&ipclock);
> +       return ret;
> +}
> +EXPORT_SYMBOL_GPL(intel_pmc_gcr_update);

-- 
With Best Regards,
Andy Shevchenko