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Message-Id: <20170405125053.6170-1-icenowy@aosc.io>
Date: Wed, 5 Apr 2017 20:50:50 +0800
From: Icenowy Zheng <icenowy@...c.io>
To: Rob Herring <robh+dt@...nel.org>,
Maxime Ripard <maxime.ripard@...e-electrons.com>,
Chen-Yu Tsai <wens@...e.org>,
Kishon Vijay Abraham I <kishon@...com>
Cc: devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com,
Icenowy Zheng <icenowy@...c.io>
Subject: [PATCH 0/3] Allwinner A64 EHCI0/OHCI0 devicetree change
This patchset contains devicetree parts of the EHCI0/OHCI0 controllers
on A64 SoC.
The first patch is a devicetree binding change, which has been planned
for 4.12; however, as Maxime Ripard suggested, it should go in 4.11
as it's part of the device's description.
The second patch added pmu0 regs and EHCI/OHCI controllers for USB0.
The third patch enabled EHCI0/OHCI0 for Pine64 board.
This patchset should go in 4.11 as Maxime Ripard suggested.
Icenowy Zheng (3):
dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64
arm64: allwinner: a64: add USB0 OHCI/EHCI related devicetree parts
arm64: allwinner: a64: enable EHCI0/OHCI0 controller for Pine64
.../devicetree/bindings/phy/sun4i-usb-phy.txt | 1 +
.../arm64/boot/dts/allwinner/sun50i-a64-pine64.dts | 8 ++++++++
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 24 ++++++++++++++++++++++
3 files changed, 33 insertions(+)
--
2.12.2
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