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Message-ID: <alpine.DEB.2.10.1704051107230.25705@vshiva-Udesk>
Date: Wed, 5 Apr 2017 11:09:05 -0700 (PDT)
From: Shivappa Vikas <vikas.shivappa@...el.com>
To: Thomas Gleixner <tglx@...utronix.de>
cc: Vikas Shivappa <vikas.shivappa@...ux.intel.com>,
vikas.shivappa@...el.com, x86@...nel.org,
linux-kernel@...r.kernel.org, hpa@...or.com, mingo@...nel.org,
peterz@...radead.org, ravi.v.shankar@...el.com,
tony.luck@...el.com, fenghua.yu@...el.com, h.peter.anvin@...el.com
Subject: Re: [PATCH 4/8] x86/intel_rct/mba: Add MBA structures and initialize
MBA
On Wed, 5 Apr 2017, Thomas Gleixner wrote:
> On Mon, 3 Apr 2017, Vikas Shivappa wrote:
>>
>> /**
>> + * struct rdt_domain - group of cpus sharing an RDT resource
>> + * @list: all instances of this resource
>> + * @id: unique id for this instance
>> + * @cpu_mask: which cpus share this resource
>> + * @ctrl_val: array of cache or mem ctrl values (indexed by CLOSID)
>> + * @new_cbm: new cbm value to be loaded
>> + * @have_new_cbm: did user provide new_cbm for this domain
>
> The version which you removed below has the kernel-doc comments correct ....
Will fix
>
>> +/**
>> * struct rdt_resource - attributes of an RDT resource
>> * @enabled: Is this feature enabled on this machine
>> * @capable: Is this feature available on this machine
>> @@ -78,6 +109,16 @@ struct rftype {
>> * @data_width: Character width of data when displaying
>> * @min_cbm_bits: Minimum number of consecutive bits to be set
>> * in a cache bit mask
>> + * @msr_update: Function pointer to update QOS MSRs
>> + * @max_delay: Max throttle delay. Delay is the hardware
>> + * understandable value for memory bandwidth.
>> + * @min_bw: Minimum memory bandwidth percentage user
>> + * can request
>> + * @bw_gran: Granularity at which the memory bandwidth
>> + * is allocated
>> + * @delay_linear: True if memory b/w delay is in linear scale
>> + * @mb_map: Mapping of memory b/w percentage to
>> + * memory b/w delay values
>> * @domains: All domains for this resource
>> * @msr_base: Base MSR address for CBMs
>> * @cache_level: Which cache level defines scope of this domain
>> @@ -94,6 +135,14 @@ struct rdt_resource {
>> int min_cbm_bits;
>> u32 default_ctrl;
>> int data_width;
>> + void (*msr_update) (struct rdt_domain *d, struct msr_param *m,
>> + struct rdt_resource *r);
>> + u32 max_delay;
>> + u32 min_bw;
>> + u32 bw_gran;
>> + u32 delay_linear;
>> + u32 *mb_map;
>
> I don't know what other weird controls will be added over time, but we are
> probably better off to have
>
> struct cache_ctrl {
> int cbm_len;
> int min_cbm_bits;
> };
>
> struct mba_ctrl {
> u32 max_delay;
> u32 min_bw;
> u32 bw_gran;
> u32 delay_linear;
> u32 *mb_map;
> };
>
> and in then in struct rdt_resource:
>
> <common fields>
> union {
> struct cache_ctrl foo;
> struct mba_ctrl bla;
> } ctrl;
>
>
> That avoids that rdt_resource becomes a hodgepodge of unrelated or even
> contradicting fields.
>
> Hmm?
Ok, makes sense. Will fix. Thought of a union when i had added a couple fields
and given up but its grown a lot now.
Thanks,
Vikas
>
> Thanks,
>
> tglx
>
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