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Message-ID: <20170405215226.GG7065@codeaurora.org>
Date: Wed, 5 Apr 2017 14:52:26 -0700
From: Stephen Boyd <sboyd@...eaurora.org>
To: gabriel.fernandez@...com
Cc: Michael Turquette <mturquette@...libre.com>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Alexandre Torgue <alexandre.torgue@...com>,
Nicolas Pitre <nico@...aro.org>, Arnd Bergmann <arnd@...db.de>,
daniel.thompson@...aro.org, andrea.merello@...il.com,
radoslaw.pietrzyk@...il.com, linux-clk@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 2/2] clk: stm32f4: fix timeout management for pll and
ready gate
On 03/16, gabriel.fernandez@...com wrote:
> From: Gabriel Fernandez <gabriel.fernandez@...com>
>
> Use a classic polling to test bit ready.
> And the shift of the bit ready of LSE & LSI were wrongs.
>
> Fixes: 861adc44d290 ("clk: stm32f4: Add LSI & LSE clocks")
>
> Signed-off-by: Gabriel Fernandez <gabriel.fernandez@...com>
> ---
Applied to clk-next
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