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Message-ID: <alpine.DEB.2.20.1704060955460.1716@nanos>
Date:   Thu, 6 Apr 2017 10:43:01 +0200 (CEST)
From:   Thomas Gleixner <tglx@...utronix.de>
To:     Dou Liyang <douly.fnst@...fujitsu.com>
cc:     x86@...nel.org, linux-kernel@...r.kernel.org, mingo@...nel.org,
        ebiederm@...ssion.com, bhe@...hat.com, hpa@...or.com,
        izumi.taku@...fujitsu.com
Subject: Re: [RFC PATCH 0/6] Unify the Interrupt Mode and setup it as soon
 as possible

On Wed, 29 Mar 2017, Dou Liyang wrote:
> The purpose of this patchset is Unifing these setup steps and executing as
> soon as possible as follows:
> 
>    start_kernel
> ---------------+
> |
> |
> |
> |     init_IRQ
> +---->---+----+
> |        |
> |        |      +--------------------+
> |        +----> | 4. init_bsp_APIC   |
> |               +--------------------+
> v
> 
> By the way, Also fix a bug about kexec[3].
> 
> 
> Some doubts, need help:
> 
> 1. Patchset has influence on IOMMU in enable_IR_x2apic(). Not sure
> it can be in advance?

That should work.

> 2. Due to 
> 
> Commit 8c3ba8d04924 ("x86, apic: ack all pending irqs when crashed/on kexec")
> 
>  ..., patchset also needs TSC and uses the "cpu_khz" in setup_local_APIC().
> And a warning[4] will be triggered when crashed/on kexec. Not sure how to
> modify?

The local APIC timer initialization cannot be run from init_IRQ().

The problem here is that CPU and TSC frequency calibration depends on the
PIT/HPET interrupt (irq 0) working for machines which cannot calibrate via
MSR/CPUID or if fast calibration via PIT fails.

So we need to split that initialization into several parts:

1) Set up the APIC/IOAPIC (including testing whether the timer interrupt
   works)

2) Calibrate TSC

3) Set up the local APIC timer

Thanks,

	tglx

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