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Message-ID: <1491774092.4166.195.camel@kernel.crashing.org>
Date: Mon, 10 Apr 2017 07:41:32 +1000
From: Benjamin Herrenschmidt <benh@...nel.crashing.org>
To: Christopher Bostic <cbostic@...ux.vnet.ibm.com>,
Joel Stanley <joel@....id.au>
Cc: Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Russell King <linux@...linux.org.uk>, rostedt@...dmis.org,
mingo@...hat.com, Greg KH <gregkh@...uxfoundation.org>,
devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
Andrew Jeffery <andrew@...id.au>,
Alistair Popple <alistair@...ple.id.au>,
"Edward A . James" <eajames@...ibm.com>,
Jeremy Kerr <jk@...abs.org>
Subject: Re: [PATCH v4 19/23] drivers/fsi: Add GPIO based FSI master
On Sun, 2017-04-09 at 16:22 -0500, Christopher Bostic wrote:
> A 3 microsecond delay is required, however, to prevent occasional issues
> during heavy FSI bus load stress testing.
> A 1 nanosecond delay using ndelay(1) had been specified prior to this
> but after looking more closely at real time performance it turned out to
> actually be roughly 1-2 microseconds. This appears to be the minimum
> resolution using the delay() linux libraries on the AST2400/2500.
> Given this, increasing delay to 3 microseconds doesn't impact
> performance much considering I can now remove the sample input delay
> based on your recommendations to re-order the two clock delays.
This is huge delays. We should consider a AST2xxx specific variant of
the backend that uses nops or similar lab-calibrated constructs
instead. Otherwise we are stuck in the kHz range, this is a >200Mhz bus
:)
I don't understand why 3us delay would thus be necessary.
Where about did you observe issues ? Could it be that you don't wait
long enough in the transitions from write to read ?
Cheers,
Ben.
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