linux-kernel - Re: [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Date:   Mon, 10 Apr 2017 12:34:05 +0200
From:   Borislav Petkov <bp@...en8.de>
To:     Piotr Luc <piotr.luc@...el.com>
Cc:     linux-edac@...r.kernel.org, Tony Luck <tony.luck@...el.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...hat.com>,
        "H. Peter Anvin" <hpa@...or.com>, x86@...nel.org,
        linux-kernel@...r.kernel.org,
        Dave Hansen <dave.hansen@...ux.intel.com>
Subject: Re: [PATCH v1] x86/mce: enable PPIN for Knights Landing/Mill

On Sat, Apr 08, 2017 at 07:20:04PM +0200, Piotr Luc wrote:
> Intel Xeon Phi processors (KNL and KNM) do support PPIN as well, so we
> add their CPUIDs to the whitelist of supported processors.
> PPIN is a unique number that allows to determine origin of the CPU,
> from now on will be logged when an mce error occur.
> 
> Signed-off-by: Piotr Luc <piotr.luc@...el.com>
> ---
>  arch/x86/kernel/cpu/mcheck/mce_intel.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/x86/kernel/cpu/mcheck/mce_intel.c b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> index 190b3e6..f1c44c3 100644
> --- a/arch/x86/kernel/cpu/mcheck/mce_intel.c
> +++ b/arch/x86/kernel/cpu/mcheck/mce_intel.c
> @@ -481,6 +481,8 @@ static void intel_ppin_init(struct cpuinfo_x86 *c)
>  	case INTEL_FAM6_BROADWELL_XEON_D:
>  	case INTEL_FAM6_BROADWELL_X:
>  	case INTEL_FAM6_SKYLAKE_X:
> +	case INTEL_FAM6_XEON_PHI_KNL:
> +	case INTEL_FAM6_XEON_PHI_KNM:
>  		if (rdmsrl_safe(MSR_PPIN_CTL, &val))
>  			return;
>  
> -- 

Applied, thanks.

-- 
Regards/Gruss,
    Boris.

Good mailing practices for 400: avoid top-posting and trim the reply.