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Date: Tue, 11 Apr 2017 20:23:19 -0300 From: Fabio Estevam <festevam@...il.com> To: Dong Aisheng <dongas86@...il.com> Cc: Stefan Agner <stefan@...er.ch>, Shawn Guo <shawnguo@...nel.org>, Sascha Hauer <kernel@...gutronix.de>, Stephen Boyd <sboyd@...eaurora.org>, Dong Aisheng <aisheng.dong@....com>, Fabio Estevam <fabio.estevam@....com>, "robh+dt@...nel.org" <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, "linux-arm-kernel@...ts.infradead.org" <linux-arm-kernel@...ts.infradead.org>, "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>, linux-clk@...r.kernel.org, linux-kernel <linux-kernel@...r.kernel.org> Subject: Re: [PATCH 2/2] ARM: dts: imx7: add USDHC NAND clock to SDHC instances On Mon, Apr 10, 2017 at 11:59 PM, Dong Aisheng <dongas86@...il.com> wrote: > This is caused by ahb_root_clk gets disabled accidently and system hangs. > > Because this patch defines ipg_root_clk earlier before its parent > (ahb_root_clk) got registered, then it will be marked as a orphan clk > temporarily. Until the parent ahb_root_clk got registered, the clk core > will reparent it to the newly found parent. (see __clk_core_init() function). > > Due to CLK_SET_RATE_PARENT flag, the ahb clk will be enabled during > set_parent operation and then disabled after that. > Then system hang cause we still get no chance to run init_on clks. > > I just send out a proper fix patch with correct register sequence. Excellent, thanks!
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