lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [thread-next>] [day] [month] [year] [list]
Date:   Thu, 13 Apr 2017 16:19:13 +0800
From:   Yunying Sun <yunying.sun@...el.com>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     Andi Kleen <ak@...ux.intel.com>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        linux-kernel@...r.kernel.org, vince@...ter.net, eranian@...gle.com,
        Arnaldo Carvalho de Melo <acme@...radead.org>,
        Yunying Sun <yunying.sun@...el.com>
Subject: [PATCH] perf/x86/intel: Add hardware cache event support for Intel Gemini Lake

Gemini Lake is a Goldmont core based Apollo Lake successor with better
CPU performance. Currently there is no hardware cache events available
if checking with "perf list cache" on Gemini Lake. Perf hardware cache
event test always fail because of this.

This patch adds INTEL_FAM6_ATOM_GEMINI_LAKE case to use same Goldmont
hardware cache events table for Gemini Lake. With this patch, below
hardware cache events are available on Gemini Lake, and perf hardware
cache event test can pass.

L1-dcache-loads
L1-dcache-stores
L1-icache-load-misses
L1-icache-loads
LLC-load-misses
LLC-loads
LLC-prefetch-misses
LLC-prefetches
LLC-store-misses
LLC-stores
branch-load-misses
branch-loads
dTLB-loads
dTLB-stores
iTLB-load-misses
iTLB-loads

Signed-off-by: Yunying Sun <yunying.sun@...el.com>
Tested-by: Yunying Sun <yunying.sun@...el.com>
---
 arch/x86/events/intel/core.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index eb1484c..f80c3a3 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -3731,6 +3731,7 @@ __init int intel_pmu_init(void)
 
 	case INTEL_FAM6_ATOM_GOLDMONT:
 	case INTEL_FAM6_ATOM_DENVERTON:
+	case INTEL_FAM6_ATOM_GEMINI_LAKE:
 		memcpy(hw_cache_event_ids, glm_hw_cache_event_ids,
 		       sizeof(hw_cache_event_ids));
 		memcpy(hw_cache_extra_regs, glm_hw_cache_extra_regs,
-- 
2.9.3

Powered by blists - more mailing lists