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Date: Thu, 13 Apr 2017 20:12:12 +0200 From: Peter Zijlstra <peterz@...radead.org> To: Yury Norov <ynorov@...iumnetworks.com> Cc: linux-kernel@...r.kernel.org, linux-arch@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, Ingo Molnar <mingo@...hat.com>, Arnd Bergmann <arnd@...db.de>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will.deacon@....com>, Jan Glauber <jglauber@...ium.com> Subject: Re: [PATCH 3/3] arm64/locking: qspinlocks and qrwlocks support On Tue, Apr 11, 2017 at 01:35:04AM +0400, Yury Norov wrote: > +++ b/arch/arm64/include/asm/qspinlock.h > @@ -0,0 +1,20 @@ > +#ifndef _ASM_ARM64_QSPINLOCK_H > +#define _ASM_ARM64_QSPINLOCK_H > + > +#include <asm-generic/qspinlock_types.h> > + > +#define queued_spin_unlock queued_spin_unlock > +/** > + * queued_spin_unlock - release a queued spinlock > + * @lock : Pointer to queued spinlock structure > + * > + * A smp_store_release() on the least-significant byte. > + */ > +static inline void queued_spin_unlock(struct qspinlock *lock) > +{ > + smp_store_release((u8 *)lock, 0); > +} I'm afraid this isn't enough for arm64. I suspect you want your own variant of queued_spin_unlock_wait() and queued_spin_is_locked() as well. Much memory ordering fun to be had there.
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