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Date: Tue, 18 Apr 2017 08:01:32 -0700 From: Andrey Smirnov <andrew.smirnov@...il.com> To: Shawn Guo <shawnguo@...nel.org> Cc: Andrey Smirnov <andrew.smirnov@...il.com>, yurovsky@...il.com, Dong Aisheng <aisheng.dong@....com>, Sascha Hauer <kernel@...gutronix.de>, Fabio Estevam <fabio.estevam@....com>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com>, Russell King <linux@...linux.org.uk>, devicetree@...r.kernel.org, linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org Subject: [PATCH v2 6/7] ARM: dts: imx7d: Add node for PCIe controller Cc: yurovsky@...il.com Cc: Dong Aisheng <aisheng.dong@....com> Cc: Shawn Guo <shawnguo@...nel.org> Cc: Sascha Hauer <kernel@...gutronix.de> Cc: Fabio Estevam <fabio.estevam@....com> Cc: Rob Herring <robh+dt@...nel.org> Cc: Mark Rutland <mark.rutland@....com> Cc: Russell King <linux@...linux.org.uk> Cc: devicetree@...r.kernel.org Cc: linux-kernel@...r.kernel.org Cc: linux-arm-kernel@...ts.infradead.org Signed-off-by: Andrey Smirnov <andrew.smirnov@...il.com> --- arch/arm/boot/dts/imx7d.dtsi | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/arch/arm/boot/dts/imx7d.dtsi b/arch/arm/boot/dts/imx7d.dtsi index f6dee41..f46814a 100644 --- a/arch/arm/boot/dts/imx7d.dtsi +++ b/arch/arm/boot/dts/imx7d.dtsi @@ -42,6 +42,7 @@ */ #include "imx7s.dtsi" +#include <dt-bindings/reset/imx7-reset.h> / { cpus { @@ -127,6 +128,42 @@ fsl,num-rx-queues=<3>; status = "disabled"; }; + + pcie: pcie@...3800000 { + compatible = "fsl,imx7d-pcie", "snps,dw-pcie"; + reg = <0x33800000 0x4000>, + <0x4ff00000 0x80000>; + reg-names = "dbi", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges = <0x81000000 0 0 0x4ff80000 0 0x00010000 /* downstream I/O */ + 0x82000000 0 0x40000000 0x40000000 0 0x0ff00000>; /* non-prefetchable memory */ + num-lanes = <1>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &intc GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &intc GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &intc GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &intc GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX7D_PCIE_CTRL_ROOT_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>, + <&clks IMX7D_PCIE_PHY_ROOT_CLK>; + clock-names = "pcie", "pcie_bus", "pcie_phy"; + assigned-clocks = <&clks IMX7D_PCIE_CTRL_ROOT_SRC>, + <&clks IMX7D_PCIE_PHY_ROOT_SRC>; + assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_250M_CLK>, + <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>; + + fsl,max-link-speed = <2>; + power-domains = <&pgc_pcie_phy>; + resets = <&src IMX7_RESET_PCIEPHY>, + <&src IMX7_RESET_PCIE_CTRL_APPS_EN>; + reset-names = "pciephy", "apps"; + status = "disabled"; + }; }; &ca_funnel_ports { -- 2.9.3
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