linux-kernel - RE: [RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on Intel only

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Message-ID: <BN6PR1201MB013189F8E8D11EE2F8AB0FCAF8190@BN6PR1201MB0131.namprd12.prod.outlook.com>
Date:   Tue, 18 Apr 2017 21:26:03 +0000
From:   "Ghannam, Yazen" <Yazen.Ghannam@....com>
To:     Borislav Petkov <bp@...e.de>
CC:     Tony Luck <tony.luck@...el.com>,
        linux-edac <linux-edac@...r.kernel.org>,
        lkml <linux-kernel@...r.kernel.org>
Subject: RE: [RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on
 Intel only

> -----Original Message-----
> From: linux-edac-owner@...r.kernel.org [mailto:linux-edac-
> owner@...r.kernel.org] On Behalf Of Borislav Petkov
> Sent: Tuesday, April 18, 2017 2:39 PM
> To: Ghannam, Yazen <Yazen.Ghannam@....com>
> Cc: Tony Luck <tony.luck@...el.com>; linux-edac <linux-
> edac@...r.kernel.org>; lkml <linux-kernel@...r.kernel.org>
> Subject: [RFC PATCH] x86/mce: Check MCi_STATUS[MISCV] for usable addr on
> Intel only
> 
> mce_usable_address() does a bunch of basic sanity checks to verify whether
> the address reported with the error is usable for further processing.
> However, we do check MCi_STATUS[MISCV] and that is not needed on AMD as
> that bit says that there's additional information about the logged error in the
> MCi_MISCj banks.
> 
> But we don't need that to know whether the address is usable - we only need
> to know whether the physical address is valid - i.e., ADDRV.
> 
>  [ On Intel the MISCV bit is needed to perform additional checks to
>    determine whether the reported address is a physical one, etc. ]
> 
> Signed-off-by: Borislav Petkov <bp@...e.de>
> Cc: "Ghannam, Yazen" <Yazen.Ghannam@....com>
> ---
> 
> Right, so I think we don't need to look at MISCV on AMD to check whether the
> address is usable because ADDRV already denotes that MCi_ADDR has the
> physical address. Yes?
> 

We definitely don't need to look at MiscV.

But the value in MCA_ADDR isn't necessarily a system physical address. It can be,
or it can be a normalized address in the case of UMCs, or it can a set/way for caches.
So it depends on the bank type and error type.

All this may just be for SMCA systems though. I need to double check.

Thanks,
Yazen