linux-kernel - Re: [PATCH 2/2] x86/fpu: Support disabling AVX and AVX512

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Message-ID: <20170419230306.GM4021@tassilo.jf.intel.com>
Date:   Wed, 19 Apr 2017 16:03:06 -0700
From:   Andi Kleen <ak@...ux.intel.com>
To:     Andi Kleen <andi@...stfloor.org>
Cc:     x86@...nel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 2/2] x86/fpu: Support disabling AVX and AVX512

Ping! Any comments on these patches? If ok please consider merging.

Thanks,
-Andi

On Sat, Mar 11, 2017 at 09:30:57AM -0800, Andi Kleen wrote:
> From: Andi Kleen <ak@...ux.intel.com>
> 
> For performance testing it is useful to be able to disable AVX
> and AVX512. User programs check in XGETBV if AVX is supported
> by the OS. If we don't initialize the XSAVE state for AVX it will
> appear as if the OS is not supporting AVX.
> 
> Implement disable options for AVX and AVX512 code in the XSAVE code.
> 
> v2: Change description. Make variable static. Remove Intel reference.
> Signed-off-by: Andi Kleen <ak@...ux.intel.com>
> ---
>  Documentation/admin-guide/kernel-parameters.txt |  3 ++
>  arch/x86/kernel/fpu/xstate.c                    | 61 +++++++++++++++++++++----
>  2 files changed, 55 insertions(+), 9 deletions(-)
> 
> diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
> index 2ba45caabada..b94ff507a48f 100644
> --- a/Documentation/admin-guide/kernel-parameters.txt
> +++ b/Documentation/admin-guide/kernel-parameters.txt
> @@ -785,6 +785,9 @@
>  	dhash_entries=	[KNL]
>  			Set number of hash buckets for dentry cache.
>  
> +	disable_avx	[X86] Disable support for AVX
> +	disable_avx512	[X86] Disable support for AVX512
> +
>  	disable_1tb_segments [PPC]
>  			Disables the use of 1TB hash page table segments. This
>  			causes the kernel to fall back to 256MB segments which
> diff --git a/arch/x86/kernel/fpu/xstate.c b/arch/x86/kernel/fpu/xstate.c
> index c24ac1efb12d..977ab03eacf7 100644
> --- a/arch/x86/kernel/fpu/xstate.c
> +++ b/arch/x86/kernel/fpu/xstate.c
> @@ -16,6 +16,20 @@
>  
>  #include <asm/tlbflush.h>
>  
> +enum xsave_features {
> +	XSAVE_X87,
> +	XSAVE_SSE,
> +	XSAVE_AVX,
> +	XSAVE_MPX_BOUNDS,
> +	XSAVE_MPX_CSR,
> +	XSAVE_AVX512_OPMASK,
> +	XSAVE_AVX512_HI256,
> +	XSAVE_AVX512_ZMM_HI256,
> +	XSAVE_PT,
> +	XSAVE_PKU,
> +	XSAVE_UNKNOWN
> +};
> +
>  /*
>   * Although we spell it out in here, the Processor Trace
>   * xfeature is completely unused.  We use other mechanisms
> @@ -41,6 +55,8 @@ static const char *xfeature_names[] =
>   */
>  u64 xfeatures_mask __read_mostly;
>  
> +static u64 xfeatures_disabled __initdata;
> +
>  static unsigned int xstate_offsets[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1};
>  static unsigned int xstate_sizes[XFEATURE_MAX]   = { [ 0 ... XFEATURE_MAX - 1] = -1};
>  static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8];
> @@ -52,6 +68,21 @@ static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8];
>   */
>  unsigned int fpu_user_xstate_size;
>  
> +static void clear_avx512(void)
> +{
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512F);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512IFMA);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512PF);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512ER);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512CD);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512DQ);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512BW);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512VL);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512VBMI);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS);
> +}
> +
>  /*
>   * Clear all of the X86_FEATURE_* bits that are unavailable
>   * when the CPU has no XSAVE support.
> @@ -64,17 +95,9 @@ void fpu__xstate_clear_all_cpu_caps(void)
>  	setup_clear_cpu_cap(X86_FEATURE_XSAVES);
>  	setup_clear_cpu_cap(X86_FEATURE_AVX);
>  	setup_clear_cpu_cap(X86_FEATURE_AVX2);
> -	setup_clear_cpu_cap(X86_FEATURE_AVX512F);
> -	setup_clear_cpu_cap(X86_FEATURE_AVX512IFMA);
> -	setup_clear_cpu_cap(X86_FEATURE_AVX512PF);
> -	setup_clear_cpu_cap(X86_FEATURE_AVX512ER);
> -	setup_clear_cpu_cap(X86_FEATURE_AVX512CD);
> -	setup_clear_cpu_cap(X86_FEATURE_AVX512DQ);
> -	setup_clear_cpu_cap(X86_FEATURE_AVX512BW);
> -	setup_clear_cpu_cap(X86_FEATURE_AVX512VL);
> +	clear_avx512();
>  	setup_clear_cpu_cap(X86_FEATURE_MPX);
>  	setup_clear_cpu_cap(X86_FEATURE_XGETBV1);
> -	setup_clear_cpu_cap(X86_FEATURE_AVX512VBMI);
>  	setup_clear_cpu_cap(X86_FEATURE_PKU);
>  	setup_clear_cpu_cap(X86_FEATURE_AVX512_4VNNIW);
>  	setup_clear_cpu_cap(X86_FEATURE_AVX512_4FMAPS);
> @@ -735,6 +758,7 @@ void __init fpu__init_system_xstate(void)
>  		goto out_disable;
>  	}
>  
> +	xfeatures_mask &= ~xfeatures_disabled;
>  	xfeatures_mask &= fpu__get_supported_xfeatures_mask();
>  
>  	/* Enable xstate instructions to be able to continue with initialization: */
> @@ -1080,3 +1104,22 @@ int copyin_to_xsaves(const void *kbuf, const void __user *ubuf,
>  
>  	return 0;
>  }
> +
> +static int __init parse_disable_avx512(char *str)
> +{
> +	xfeatures_disabled |= BIT(XSAVE_AVX512_OPMASK) |
> +			      BIT(XSAVE_AVX512_HI256) |
> +			      BIT(XSAVE_AVX512_ZMM_HI256);
> +	clear_avx512();
> +	return 0;
> +}
> +early_param("disable_avx512", parse_disable_avx512);
> +
> +static int __init parse_disable_avx(char *str)
> +{
> +	xfeatures_disabled |= BIT(XSAVE_AVX);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX);
> +	setup_clear_cpu_cap(X86_FEATURE_AVX2);
> +	return parse_disable_avx512(NULL);
> +}
> +early_param("disable_avx", parse_disable_avx);
> -- 
> 2.9.3
>