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Message-ID: <4966c67b-886f-45c6-a38b-3dc2f1aac6e2@US01WEHTC2.internal.synopsys.com>
Date: Wed, 19 Apr 2017 17:40:05 +0400
From: Razmik Karapetyan <Razmik.Karapetyan@...opsys.com>
To: John Youn <John.Youn@...opsys.com>,
Felipe Balbi <balbi@...nel.org>,
"Greg Kroah-Hartman" <gregkh@...uxfoundation.org>,
<linux-usb@...r.kernel.org>, <linux-kernel@...r.kernel.org>
CC: Razmik Karapetyan <Razmik.Karapetyan@...opsys.com>
Subject: [PATCH v2 1/3] usb: dwc2: Define PCGCCTL1 register in hw.h
PCGCCTL1 (Power and Clock Control) register will be used
for controlling the core`s active clock gating feature.
Signed-off-by: Razmik Karapetyan <razmik@...opsys.com>
---
drivers/usb/dwc2/hw.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/usb/dwc2/hw.h b/drivers/usb/dwc2/hw.h
index 4592012..b726701 100644
--- a/drivers/usb/dwc2/hw.h
+++ b/drivers/usb/dwc2/hw.h
@@ -643,6 +643,10 @@
#define PCGCTL_GATEHCLK BIT(1)
#define PCGCTL_STOPPCLK BIT(0)
+#define PCGCCTL1 HSOTG_REG(0xe04)
+#define PCGCCTL1_TIMER (0x3 << 1)
+#define PCGCCTL1_GATEEN BIT(0)
+
#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000))
/* Host Mode Registers */
--
2.7.4
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