lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20170424132835.berjg6jakizu5s4v@home.goodmis.org>
Date:   Mon, 24 Apr 2017 09:28:36 -0400
From:   Steven Rostedt <rostedt@...dmis.org>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     LKML <linux-kernel@...r.kernel.org>,
        Thomas Gleixner <tglx@...utronix.de>,
        Ingo Molnar <mingo@...nel.org>,
        Clark Williams <williams@...hat.com>,
        Daniel Bristot de Oliveira <bristot@...hat.com>,
        John Kacur <jkacur@...hat.com>
Subject: Re: [RFC][PATCH tip/sched/core] sched/rt: Simplify the IPI rt
 balancing logic

On Mon, Apr 24, 2017 at 02:52:00PM +0200, Peter Zijlstra wrote:
> On Mon, Apr 24, 2017 at 08:43:18AM -0400, Steven Rostedt wrote:
> > On Mon, 24 Apr 2017 10:51:54 +0200
> > Peter Zijlstra <peterz@...radead.org> wrote:
> > 
> > > On Fri, Apr 21, 2017 at 10:49:29PM -0400, Steven Rostedt wrote:
> > > > When a CPU schedules in a lower priority task and wants to make sure
> > > > overloaded CPUs know about it. It increments the rto_loop_next. Then it does
> > > > an atomic_inc_return() on rto_loop_start. If the returned value is not "1",
> > > > then it does atomic_dec() on rt_loop_start and returns. If the value is "1",
> > > > then it will take the rto_lock to synchronize with a possible IPI being sent
> > > > around to the overloaded CPUs.  
> > > 
> > > > +	start = atomic_inc_return(&rq->rd->rto_loop_start);
> > > > +	if (start != 1)
> > > > +		goto out;  
> > > 
> > > > +out:
> > > > +	atomic_dec(&rq->rd->rto_loop_start);  
> > > 
> > > 
> > > Did you just write a very expensive test-and-set trylock?
> > 
> > Probably. I didn't know we had a generic one. Where is it?
> > 
> 
> There isn't. What I was getting at though is that something like:
> 
> static inline bool rto_start_trylock(atomic_t *v)
> {
> 	int zero = 0;
> 	return atomic_try_cmpxchg(v, &zero, 1);

To keep the same semantics of spin_trylock(), should we:

  return !atomic_cmpxchg(v, &zero, 1);

as the old value of zero means we got it.

BTW, I don't see any atomic_try_cmpxchg().


> }
> 
> static void rto_start_unlock(atomic_t *v)
> {
> 	atomic_set_release(v, 0);
> }
> 
> Is more: clearer, faster and correct.
> 
> 
> Clearer as that it better describes what it does, faster as that you
> only have a single atomic, and more correct because it does a RELEASE in
> the case we care about.
> 

Yes, I like the above. Thanks, I will add.

-- Steve

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ