linux-kernel - Re: [PATCH V3 4/4] soc/tegra: pmc: Use the new reset APIs to manage reset controllers

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Message-ID: <5e0c2030-ad96-15fc-1dc4-db6cd11d52c3@codeaurora.org>
Date:   Tue, 25 Apr 2017 16:36:30 +0530
From:   Vivek Gautam <vivek.gautam@...eaurora.org>
To:     Jon Hunter <jonathanh@...dia.com>
Cc:     Philipp Zabel <p.zabel@...gutronix.de>, swarren@...dotorg.org,
        balbi@...nel.org, linux-kernel@...r.kernel.org,
        linux-tegra@...r.kernel.org, linux-usb@...r.kernel.org,
        thierry.reding@...il.com, gregkh@...uxfoundation.org,
        linux-arm-msm@...r.kernel.org, Thierry Reding <treding@...dia.com>
Subject: Re: [PATCH V3 4/4] soc/tegra: pmc: Use the new reset APIs to manage
 reset controllers



On 04/25/2017 04:24 PM, Jon Hunter wrote:
> On 25/04/17 11:33, Philipp Zabel wrote:
>> On Tue, 2017-04-25 at 11:05 +0100, Jon Hunter wrote:
>>> On 25/04/17 05:15, Vivek Gautam wrote:
>>>> On 04/24/2017 06:15 PM, Jon Hunter wrote:
>>>>> On 18/04/17 12:21, Vivek Gautam wrote:
>>>>>> Make use of reset_control_array_*() set of APIs to manage
>>>>>> an array of reset controllers available with the device.
>>>>> Before we apply this patch, I need to check to see if the order of the
>>>>> resets managed by the PMC driver matter. Today the order of the resets
>>>>> is determined by the order they appear in the DT node and although the
>>>>> new APIs work in the same way they do not guarantee this. So let me
>>>>> check to see if we can any concerns about ordering here. Otherwise would
>>>>> be nice to use these APIs.
>>>> Right, that will be perfect.
>>> So I don't see any restrictions here and so I think this change is fine.
>> Thank you for checking.
>>
>>> BTW, for the DT case, is there any reason why we don't just say the
>>> order will be determine by the order the resets are list in the DT node?
>> I'd rather not make any promises, so I don't have to care about keeping
>> them. This makes it easier to think about and allows for more freedom in
>> changing the core code if needed.
>>
>> What if in the future there is a use case for enabling a bunch of resets
>> by flipping a number of bits in a single register at the same time? Or
>> if people accidentally depend on the ordering when in reality there is a
>> small delay necessary between assertions that just happens to be hidden
>> by the framework overhead?
>>
>> If there is a use case for an array of reset controls that must be
>> (de)asserted in a fixed order and doesn't need any delay between the
>> steps and is not suitable to be described by named resets for some
>> reason, we can discuss this. Until then, I'm happy that tegra pmc can
>> handle arrays without any particular ordering.
> OK, makes sense.

Thanks Jon for testing this.

Best Regards
Vivek
>
> Thanks
> Jon
>

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