linux-kernel - Re: [PATCH v7 1/6] platform/x86: intel_pmc

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-ID: <c1a6ee3d-ded0-fc6d-3f3e-d7f8b4c2e323@linux.intel.com>
Date:   Tue, 25 Apr 2017 10:34:43 -0700
From:   sathyanarayanan kuppuswamy 
        <sathyanarayanan.kuppuswamy@...ux.intel.com>
To:     Andy Shevchenko <andy.shevchenko@...il.com>
Cc:     Andy Shevchenko <andy@...radead.org>,
        Zha Qipeng <qipeng.zha@...el.com>,
        "dvhart@...radead.org" <dvhart@...radead.org>,
        Guenter Roeck <linux@...ck-us.net>,
        Wim Van Sebroeck <wim@...ana.be>,
        Sathyanarayanan Kuppuswamy Natarajan <sathyaosid@...il.com>,
        David Box <david.e.box@...ux.intel.com>,
        Rajneesh Bhardwaj <rajneesh.bhardwaj@...el.com>,
        Platform Driver <platform-driver-x86@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        linux-watchdog@...r.kernel.org
Subject: Re: [PATCH v7 1/6] platform/x86: intel_pmc_ipc: fix gcr offset



On 04/25/2017 06:29 AM, Andy Shevchenko wrote:
> On Mon, Apr 10, 2017 at 1:00 AM, Kuppuswamy Sathyanarayanan
> <sathyanarayanan.kuppuswamy@...ux.intel.com> wrote:
>> According to Broxton APL spec, PMC MIMO resources for Global Control
>> Registers(GCR) are located at 4K(0x1000) offset from IPC base address.
>> In this driver, PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR
>> region base address from IPC base address and its current value of
>> 0x1008 is incorrect because it points to location for PMC_CFG register
>> and not the GCR base address itself.
>>
>> GCR Base = IPC1 Base + 0x1000.
>>
>> This patch fixes this offset issue.
> The whole series has been pushed to testing, thanks.
Thanks Andy.
>
>> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
>> ---
>>   drivers/platform/x86/intel_pmc_ipc.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> Changes since v6:
>>   *  Updated commit message
>>
>> Changes since v5:
>>   *  None
>>
>> Changes since v4:
>>   *  None
>>
>> Changes since v3:
>>   * Updated the commit history
>>
>> diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c
>> index 0651d47..0a33592 100644
>> --- a/drivers/platform/x86/intel_pmc_ipc.c
>> +++ b/drivers/platform/x86/intel_pmc_ipc.c
>> @@ -82,7 +82,7 @@
>>   /* exported resources from IFWI */
>>   #define PLAT_RESOURCE_IPC_INDEX                0
>>   #define PLAT_RESOURCE_IPC_SIZE         0x1000
>> -#define PLAT_RESOURCE_GCR_OFFSET       0x1008
>> +#define PLAT_RESOURCE_GCR_OFFSET       0x1000
>>   #define PLAT_RESOURCE_GCR_SIZE         0x1000
>>   #define PLAT_RESOURCE_BIOS_DATA_INDEX  1
>>   #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2
>> --
>> 2.7.4
>>
>
>

-- 
Sathyanarayanan Kuppuswamy
Android kernel developer