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Message-ID: <CA5F6A4B62957246A95956419746064359681D98@IRSMSX106.ger.corp.intel.com>
Date: Wed, 26 Apr 2017 06:41:58 +0000
From: "Lofstedt, Marta" <marta.lofstedt@...el.com>
To: Peter Zijlstra <peterz@...radead.org>
CC: "tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...nel.org" <mingo@...nel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"ville.syrjala@...ux.intel.com" <ville.syrjala@...ux.intel.com>,
"daniel.lezcano@...aro.org" <daniel.lezcano@...aro.org>,
"Wysocki, Rafael J" <rafael.j.wysocki@...el.com>,
"martin.peres@...ux.intel.com" <martin.peres@...ux.intel.com>,
"pasha.tatashin@...cle.com" <pasha.tatashin@...cle.com>,
"daniel.vetter@...ll.ch" <daniel.vetter@...ll.ch>
Subject: RE: [PATCH 0/9] sched_clock fixes
For bisecting the regression we ran 14 test for 50 repetitions.
Before the bisected regression:
commit 7b09cc5a9debc86c903c2eff8f8a1fdef773c649
Author: Pavel Tatashin <pasha.tatashin@...cle.com>
Date: Wed Mar 22 16:24:17 2017 -0400
sched/clock: Fix broken stable to unstable transfer
there was ~0 failing test on the Core2 machine.
After regression ~350 failing tests.
With your patch-set ~15 failing tests.
To be honest, I must say that these test used to give unstable results on the Core2. But some time ago, the results magically stabilized at ~0 fails, by timing related fixes for other issues. Ville Syrjala now has a patch-set that we believe really solves the graphics parts of the issue. However, I believe that your patch-set still improves the situation related to the tsc instability of the Core2.
/Marta
> -----Original Message-----
> From: Peter Zijlstra [mailto:peterz@...radead.org]
> Sent: Tuesday, April 25, 2017 4:45 PM
> To: Lofstedt, Marta <marta.lofstedt@...el.com>
> Cc: tglx@...utronix.de; mingo@...nel.org; linux-kernel@...r.kernel.org;
> ville.syrjala@...ux.intel.com; daniel.lezcano@...aro.org; Wysocki, Rafael J
> <rafael.j.wysocki@...el.com>; martin.peres@...ux.intel.com;
> pasha.tatashin@...cle.com; daniel.vetter@...ll.ch
> Subject: Re: [PATCH 0/9] sched_clock fixes
>
> On Tue, Apr 25, 2017 at 09:31:40AM +0000, Lofstedt, Marta wrote:
> > Hi Peterz,
> >
> > I tested your patch-set on the same Core2 machine as where we
> discovered the regression.
> > With the tsc=unstable boot param that passrate has improved significantly;
> 350 fails -> 15 fails.
>
> So is that the same as before, or still worse? I don't really have a handle on
> what your benchmark is here, nor what how 'good' is defined.
>
> If its still worse than before, I'm completely confused. Because with
> "tsc=unstable" the patch you fingered is a complete no-op (__gtod_offset
> == 0).
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