linux-kernel - Re: [PATCH 1/4] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA

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Message-ID: <CAK8P3a2PTrDEKbvGRDcq6dhDaALbEQbUwO-TpjricgJPREFK=g@mail.gmail.com>
Date:   Thu, 4 May 2017 10:47:11 +0200
From:   Arnd Bergmann <arnd@...db.de>
To:     Benoît Thébaudeau <benoit@...stem.com>
Cc:     Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        linux-mmc@...r.kernel.org, Ulf Hansson <ulf.hansson@...aro.org>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Fabio Estevam <fabio.estevam@....com>,
        joancarles <joancarles@...ngenieria.es>,
        Eric Bénard <eric@...rea.com>,
        Wolfram Sang <wsa@...-dreams.de>
Subject: Re: [PATCH 1/4] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR

On Wed, May 3, 2017 at 12:05 PM, Benoît Thébaudeau <benoit@...stem.com> wrote:
> The eSDHC can only DMA from 32-bit-aligned addresses.
>
> This fixes the following test cases of mmc_test:
>   11:   Badly aligned write
>   12:   Badly aligned read
>   13:   Badly aligned multi-block write
>   14:   Badly aligned multi-block read
>
> Signed-off-by: Benoît Thébaudeau <benoit@...stem.com>

Is this the right description? I thought that SDHCI_QUIRK_32BIT_DMA_ADDR
was for devices that cannot address high memory above 0xffffffff, rather than
requiring a specific alignment.

If this is indeed an address range problem rather than an alignment problem,
are you sure it is the SD controller that is wrong here, rather than having a
64-bit DMA capable  SDHCI connected to a 32-bit parent bus? In the
latter case, the dma-ranges property in the parent bus should limit
the addressing, not the device.

      Arnd