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Date: Fri, 5 May 2017 11:17:18 -0700 From: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com> To: Ingo Molnar <mingo@...hat.com>, Thomas Gleixner <tglx@...utronix.de>, "H. Peter Anvin" <hpa@...or.com>, Andy Lutomirski <luto@...nel.org>, Borislav Petkov <bp@...e.de> Cc: Peter Zijlstra <peterz@...radead.org>, Andrew Morton <akpm@...ux-foundation.org>, Brian Gerst <brgerst@...il.com>, Chris Metcalf <cmetcalf@...lanox.com>, Dave Hansen <dave.hansen@...ux.intel.com>, Paolo Bonzini <pbonzini@...hat.com>, Liang Z Li <liang.z.li@...el.com>, Masami Hiramatsu <mhiramat@...nel.org>, Huang Rui <ray.huang@....com>, Jiri Slaby <jslaby@...e.cz>, Jonathan Corbet <corbet@....net>, "Michael S. Tsirkin" <mst@...hat.com>, Paul Gortmaker <paul.gortmaker@...driver.com>, Vlastimil Babka <vbabka@...e.cz>, Chen Yucong <slaoub@...il.com>, Alexandre Julliard <julliard@...ehq.org>, Stas Sergeev <stsp@...t.ru>, Fenghua Yu <fenghua.yu@...el.com>, "Ravi V. Shankar" <ravi.v.shankar@...el.com>, Shuah Khan <shuah@...nel.org>, linux-kernel@...r.kernel.org, x86@...nel.org, linux-msdos@...r.kernel.org, wine-devel@...ehq.org, Ricardo Neri <ricardo.neri-calderon@...ux.intel.com>, Tony Luck <tony.luck@...el.com> Subject: [PATCH v7 20/26] x86/cpufeature: Add User-Mode Instruction Prevention definitions User-Mode Instruction Prevention is a security feature present in new Intel processors that, when set, prevents the execution of a subset of instructions if such instructions are executed in user mode (CPL > 0). Attempting to execute such instructions causes a general protection exception. The subset of instructions comprises: * SGDT - Store Global Descriptor Table * SIDT - Store Interrupt Descriptor Table * SLDT - Store Local Descriptor Table * SMSW - Store Machine Status Word * STR - Store Task Register This feature is also added to the list of disabled-features to allow a cleaner handling of build-time configuration. Cc: Andy Lutomirski <luto@...nel.org> Cc: Andrew Morton <akpm@...ux-foundation.org> Cc: H. Peter Anvin <hpa@...or.com> Cc: Borislav Petkov <bp@...e.de> Cc: Brian Gerst <brgerst@...il.com> Cc: Chen Yucong <slaoub@...il.com> Cc: Chris Metcalf <cmetcalf@...lanox.com> Cc: Dave Hansen <dave.hansen@...ux.intel.com> Cc: Fenghua Yu <fenghua.yu@...el.com> Cc: Huang Rui <ray.huang@....com> Cc: Jiri Slaby <jslaby@...e.cz> Cc: Jonathan Corbet <corbet@....net> Cc: Michael S. Tsirkin <mst@...hat.com> Cc: Paul Gortmaker <paul.gortmaker@...driver.com> Cc: Peter Zijlstra <peterz@...radead.org> Cc: Ravi V. Shankar <ravi.v.shankar@...el.com> Cc: Shuah Khan <shuah@...nel.org> Cc: Vlastimil Babka <vbabka@...e.cz> Cc: Tony Luck <tony.luck@...el.com> Cc: Paolo Bonzini <pbonzini@...hat.com> Cc: Liang Z. Li <liang.z.li@...el.com> Cc: Alexandre Julliard <julliard@...ehq.org> Cc: Stas Sergeev <stsp@...t.ru> Cc: x86@...nel.org Cc: linux-msdos@...r.kernel.org Signed-off-by: Ricardo Neri <ricardo.neri-calderon@...ux.intel.com> --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/disabled-features.h | 8 +++++++- arch/x86/include/uapi/asm/processor-flags.h | 2 ++ 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 2701e5f..f1d61d2 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -289,6 +289,7 @@ /* Intel-defined CPU features, CPUID level 0x00000007:0 (ecx), word 16 */ #define X86_FEATURE_AVX512VBMI (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/ +#define X86_FEATURE_UMIP (16*32+ 2) /* User Mode Instruction Protection */ #define X86_FEATURE_PKU (16*32+ 3) /* Protection Keys for Userspace */ #define X86_FEATURE_OSPKE (16*32+ 4) /* OS Protection Keys Enable */ #define X86_FEATURE_AVX512_VPOPCNTDQ (16*32+14) /* POPCNT for vectors of DW/QW */ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index 5dff775..7adaef7 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -16,6 +16,12 @@ # define DISABLE_MPX (1<<(X86_FEATURE_MPX & 31)) #endif +#ifdef CONFIG_X86_INTEL_UMIP +# define DISABLE_UMIP 0 +#else +# define DISABLE_UMIP (1<<(X86_FEATURE_UMIP & 31)) +#endif + #ifdef CONFIG_X86_64 # define DISABLE_VME (1<<(X86_FEATURE_VME & 31)) # define DISABLE_K6_MTRR (1<<(X86_FEATURE_K6_MTRR & 31)) @@ -61,7 +67,7 @@ #define DISABLED_MASK13 0 #define DISABLED_MASK14 0 #define DISABLED_MASK15 0 -#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57) +#define DISABLED_MASK16 (DISABLE_PKU|DISABLE_OSPKE|DISABLE_LA57|DISABLE_UMIP) #define DISABLED_MASK17 0 #define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 18) diff --git a/arch/x86/include/uapi/asm/processor-flags.h b/arch/x86/include/uapi/asm/processor-flags.h index 567de50..d2c2af8 100644 --- a/arch/x86/include/uapi/asm/processor-flags.h +++ b/arch/x86/include/uapi/asm/processor-flags.h @@ -104,6 +104,8 @@ #define X86_CR4_OSFXSR _BITUL(X86_CR4_OSFXSR_BIT) #define X86_CR4_OSXMMEXCPT_BIT 10 /* enable unmasked SSE exceptions */ #define X86_CR4_OSXMMEXCPT _BITUL(X86_CR4_OSXMMEXCPT_BIT) +#define X86_CR4_UMIP_BIT 11 /* enable UMIP support */ +#define X86_CR4_UMIP _BITUL(X86_CR4_UMIP_BIT) #define X86_CR4_VMXE_BIT 13 /* enable VMX virtualization */ #define X86_CR4_VMXE _BITUL(X86_CR4_VMXE_BIT) #define X86_CR4_SMXE_BIT 14 /* enable safer mode (TXT) */ -- 2.9.3
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