linux-kernel - [RFC PATCH v3 05/12] x86/ioapic: Refactor the delay logic in timer_irq

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Message-ID: <1494423889-25799-6-git-send-email-douly.fnst@cn.fujitsu.com>
Date:   Wed, 10 May 2017 21:44:42 +0800
From:   Dou Liyang <douly.fnst@...fujitsu.com>
To:     <x86@...nel.org>, <linux-kernel@...r.kernel.org>
CC:     <tglx@...utronix.de>, <mingo@...nel.org>, <hpa@...or.com>,
        <ebiederm@...ssion.com>, <bhe@...hat.com>,
        <izumi.taku@...fujitsu.com>, Dou Liyang <douly.fnst@...fujitsu.com>
Subject: [RFC PATCH v3 05/12] x86/ioapic: Refactor the delay logic in timer_irq_works()

Kernel use timer_irq_works() to detects the timer IRQs. It calls
mdelay(10) to delay ten ticks and checks whether the timer IRQs work
or not. The mdelay() depends on the loops_per_jiffy which is set up
in calibrate_delay(). And in "notsc" case, calibrating delay also
should make sure the timer IRQs work well.

Now, initializing interrupt mode behind timer init makes the
timer_irq_works() in advance of calibrate_delay(). the mdelay()
doesn't work well in timer_irq_works().

Refactor the delay logic by waiting for some cycles. At the system
With X86_FEATURE_TSC, Use rdtsc(), others will call __delay() directly.

Signed-off-by: Dou Liyang <douly.fnst@...fujitsu.com>
---
v2 --> v3:
  Find a new way to for waiting.
  Reference to the realization of hpet_clocksource_register() by Thomas.

 arch/x86/kernel/apic/io_apic.c | 46 ++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 44 insertions(+), 2 deletions(-)

diff --git a/arch/x86/kernel/apic/io_apic.c b/arch/x86/kernel/apic/io_apic.c
index 347bb9f..a63c19e 100644
--- a/arch/x86/kernel/apic/io_apic.c
+++ b/arch/x86/kernel/apic/io_apic.c
@@ -1607,6 +1607,44 @@ static int __init notimercheck(char *s)
 }
 __setup("no_timer_check", notimercheck);
 
+static void delay_with_tsc(void)
+{
+	unsigned long long start, now;
+	unsigned long ticks = jiffies;
+
+	start = rdtsc();
+
+	/*
+	 * We don't know the TSC frequency yet, but waiting for
+	 * 40000000000/HZ TSC cycles is safe:
+	 * 4 GHz == 10 jiffies
+	 * 1 GHz == 40 jiffies
+	 */
+	do {
+		rep_nop();
+		now = rdtsc();
+	} while ((now - start) < 40000000000UL / HZ &&
+		time_before_eq(jiffies, ticks + 4));
+}
+
+static void delay_without_tsc(void)
+{
+	int band = 1;
+	unsigned long ticks = jiffies;
+
+	/*
+	 * We don't know any frequency yet, but waiting for
+	 * 40940000000/HZ cycles is safe:
+	 * 4 GHz == 10 jiffies
+	 * 1 GHz == 40 jiffies
+	 * 1 << 1 + 1 << 2 +...+ 1 << 11 = 4094
+	 */
+	do {
+		__delay(((1 << band++) * 10000000UL) / HZ);
+	} while (band < 12 && time_before_eq(jiffies, ticks + 4));
+}
+
+
 /*
  * There is a nasty bug in some older SMP boards, their mptable lies
  * about the timer IRQ. We do the following to work around the situation:
@@ -1625,8 +1663,12 @@ static int __init timer_irq_works(void)
 
 	local_save_flags(flags);
 	local_irq_enable();
-	/* Let ten ticks pass... */
-	mdelay((10 * 1000) / HZ);
+
+	if (boot_cpu_has(X86_FEATURE_TSC))
+		delay_with_tsc();
+	else
+		delay_without_tsc();
+
 	local_irq_restore(flags);
 
 	/*
-- 
2.5.5