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Date:   Fri, 12 May 2017 10:39:12 +0200
From:   Paolo Bonzini <>
To:     Xiao Guangrong <>,,
Cc:     Peter Feiner <>,
        David Matlack <>,
        Radim Krčmář <>,
        Xiao Guangrong <>,
        Wanpeng Li <>,
Subject: Re: [PATCH 2/2] KVM: nVMX: fix nEPT handling of guest page table

On 12/05/2017 09:38, Xiao Guangrong wrote:
> CC Kevin as i am not sure if Intel is aware of this issue, it
> breaks other hypervisors, e.g, Xen, as swell.

It's actually more complicated.

When EPT A/D bits are disabled, reads of the page tables behave as
described in the manual; writes have both bit 0 and bit 1 set, while the
manual suggests only bit 1 is set.

Peter and David convinced me that it's a hypervisor bug, and I'm not
surprised that Xen has the same issue.  You have to disable EPT A/D bits
for shadow EPT page tables when the L1 hypervisor is not using them.


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