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Message-Id: <20170515173504.11337-1-eric@anholt.net>
Date: Mon, 15 May 2017 10:35:04 -0700
From: Eric Anholt <eric@...olt.net>
To: Lee Jones <lee@...nel.org>,
Florian Fainelli <f.fainelli@...il.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...eaurora.org>
Cc: linux-rpi-kernel@...ts.infradead.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
Stefan Wahren <stefan.wahren@...e.com>,
bcm-kernel-feedback-list@...adcom.com, linux-clk@...r.kernel.org,
Phil Elwell <phil@...pberrypi.org>,
Eric Anholt <eric@...olt.net>
Subject: [PATCH] clk: bcm2835: Correct the prediv logic
From: Phil Elwell <phil@...pberrypi.org>
If a clock has the prediv flag set, both the integer and fractional
parts must be scaled when calculating the resulting frequency.
Signed-off-by: Phil Elwell <phil@...pberrypi.org>
Signed-off-by: Eric Anholt <eric@...olt.net>
---
While this is a bugfix, I haven't put a "Fixes:" line in here to get
it automatically backported to stable. We had trouble with the
out-of-tree DSI panel driver, at least: Our old set_rate() didn't
work, because the new PLL was just barely too fast to get the integer
PLL divider we needed. We may run into similar troubles
elsewhere. --anholt
drivers/clk/bcm/clk-bcm2835.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
index 025853870619..7a35df6b45bd 100644
--- a/drivers/clk/bcm/clk-bcm2835.c
+++ b/drivers/clk/bcm/clk-bcm2835.c
@@ -616,8 +616,10 @@ static unsigned long bcm2835_pll_get_rate(struct clk_hw *hw,
using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
data->ana->fb_prediv_mask;
- if (using_prediv)
+ if (using_prediv) {
ndiv *= 2;
+ fdiv *= 2;
+ }
return bcm2835_pll_rate_from_divisors(parent_rate, ndiv, fdiv, pdiv);
}
--
2.11.0
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