linux-kernel - [PATCH 4.9 144/164] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT

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Message-Id: <20170523200913.302131196@linuxfoundation.org>
Date:   Tue, 23 May 2017 22:09:21 +0200
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Huacai Chen <chenhc@...ote.com>,
        John Crispin <john@...ozen.org>,
        "Steven J . Hill" <Steven.Hill@...iumnetworks.com>,
        Fuxin Zhang <zhangfx@...ote.com>,
        Zhangjin Wu <wuzhangjin@...il.com>, linux-mips@...ux-mips.org,
        Ralf Baechle <ralf@...ux-mips.org>
Subject: [PATCH 4.9 144/164] MIPS: Loongson-3: Select MIPS_L1_CACHE_SHIFT_6

4.9-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Huacai Chen <chenhc@...ote.com>

commit 17c99d9421695a0e0de18bf1e7091d859e20ec1d upstream.

Some newer Loongson-3 have 64 bytes cache lines, so select
MIPS_L1_CACHE_SHIFT_6.

Signed-off-by: Huacai Chen <chenhc@...ote.com>
Cc: John Crispin <john@...ozen.org>
Cc: Steven J . Hill <Steven.Hill@...iumnetworks.com>
Cc: Fuxin Zhang <zhangfx@...ote.com>
Cc: Zhangjin Wu <wuzhangjin@...il.com>
Cc: linux-mips@...ux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/15755/
Signed-off-by: Ralf Baechle <ralf@...ux-mips.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>

---
 arch/mips/Kconfig |    1 +
 1 file changed, 1 insertion(+)

--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -1368,6 +1368,7 @@ config CPU_LOONGSON3
 	select WEAK_ORDERING
 	select WEAK_REORDERING_BEYOND_LLSC
 	select MIPS_PGD_C0_CONTEXT
+	select MIPS_L1_CACHE_SHIFT_6
 	select GPIOLIB
 	help
 		The Loongson 3 processor implements the MIPS64R2 instruction