lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Message-ID: <20170523152339.ngjr6djukrrqcvxm@rob-hp-laptop>
Date:   Tue, 23 May 2017 10:23:39 -0500
From:   Rob Herring <robh@...nel.org>
To:     Gregory CLEMENT <gregory.clement@...e-electrons.com>
Cc:     Stephen Boyd <sboyd@...eaurora.org>,
        Mike Turquette <mturquette@...libre.com>,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        Jason Cooper <jason@...edaemon.net>,
        Andrew Lunn <andrew@...n.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        Nadav Haklai <nadavh@...vell.com>,
        Kostya Porotchkin <kostap@...vell.com>,
        Neta Zur Hershkovits <neta@...vell.com>,
        Marcin Wojtas <mw@...ihalf.com>,
        Omri Itach <omrii@...vell.com>,
        Shadi Ammouri <shadi@...vell.com>
Subject: Re: [PATCH 5/7] clk: mvebu: cp110: add sdio clock to cp-110 system
 controller

On Fri, May 19, 2017 at 05:55:23PM +0200, Gregory CLEMENT wrote:
> From: Konstantin Porotchkin <kostap@...vell.com>
> 
> This commit updates the CP110 system controller driver to add the
> definition for a missing clock.
> 
> The SDIO clock is dedicated driving the SDHCI interface and its frequency
> is 400MHz (2/5 of PLL source clock).
> 
> The SDIO interface should be bound to this clock and not the core clock
> as in the older code.
> Using the wrong clock lead to a maximum SDHCI frequency of 250 Mhz, while
> the HW really supports up to 400 Mhz.
> 
> This patch also fixes the NAND clock relationship documentation.
> 
> Signed-off-by: Konstantin Porotchkin <kostap@...vell.com>
> [gregory.clement@...e-electrons.com:
> - use sdio instead of emmc to name the clock
> - update binding documentation]
> Signed-off-by: Gregory CLEMENT <gregory.clement@...e-electrons.com>
> Reviewed-by: Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
> ---
>  Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt |  1 +
>  drivers/clk/mvebu/cp110-system-controller.c                                | 28 +++++++++++++++++++++++-----
>  2 files changed, 24 insertions(+), 5 deletions(-)

Acked-by: Rob Herring <robh@...nel.org>

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ