linux-kernel - [Q] What about PCI mmio access alignment?

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [thread-next>] [day] [month] [year] [list]

Message-ID: <20170525101256.GA12183@intel.com>
Date:   Thu, 25 May 2017 18:12:57 +0800
From:   "Du, Changbin" <changbin.du@...el.com>
To:     linux-pci@...r.kernel.org
Cc:     changbin.du@...el.com, linux-kernel@...r.kernel.org
Subject: [Q] What about PCI mmio access alignment?

Hi, guys,
I have a basic quesion about the alignment when access PCI bar mmio space. Is
the address accessed must be DW aligned and count must be DW aligned?

As far as I know, The address field of TLB ignore lower 2 bits and the unit of
length field also is DW. So does it mean above question is Yes? Else will CPU
handle unaligned access for mmio space?

I want to know wether below access illegal or not:
  - readb(bar0)
  - readb(bar0 + 1)
  - readl(bar0)

Thanks,
Changbin Du

Download attachment "signature.asc" of type "application/pgp-signature" (474 bytes)