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Message-ID: <20170526082859.GS10827@nuc-i3427.alporthouse.com>
Date: Fri, 26 May 2017 09:28:59 +0100
From: Chris Wilson <chris@...is-wilson.co.uk>
To: Xiaoguang Chen <xiaoguang.chen@...el.com>,
alex.williamson@...hat.com, kraxel@...hat.com,
intel-gfx@...ts.freedesktop.org, linux-kernel@...r.kernel.org,
zhenyuw@...ux.intel.com, zhiyuan.lv@...el.com,
intel-gvt-dev@...ts.freedesktop.org, zhi.a.wang@...el.com,
kevin.tian@...el.com
Subject: Re: [Intel-gfx] [PATCH v5 4/5] drm/i915/gvt: Dmabuf support for GVT-g
On Thu, May 25, 2017 at 02:28:25PM +0100, Chris Wilson wrote:
> On Tue, May 23, 2017 at 06:32:00PM +0800, Xiaoguang Chen wrote:
> > + gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
> > + (fb_gma >> PAGE_SHIFT);
> > + for_each_sg(st->sgl, sg, fb_size, i) {
> > + sg->offset = 0;
> > + sg->length = PAGE_SIZE;
> > + sg_dma_address(sg) =
> > + GEN8_DECODE_PTE(readq(>t_entries[i]));
> > + sg_dma_len(sg) = PAGE_SIZE;
>
> This assumes that the entries are PAGE_SIZE. This will not remain true.
Ok, we will only be supporting different page sizes for ppgtt. However,
it is probably better to use I915_GTT_PAGE_SIZE to match our insertions.
-Chris
--
Chris Wilson, Intel Open Source Technology Centre
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