lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Sun, 28 May 2017 16:09:52 +0100
From:   Jonathan Cameron <jic23@...nel.org>
To:     Nikita Yushchenko <nikita.yoush@...entembedded.com>
Cc:     Shawn Guo <shawnguo@...nel.org>, Andrew Lunn <andrew@...n.ch>,
        Stefan Agner <stefan@...er.ch>,
        Mark Rutland <mark.rutland@....com>,
        devicetree@...r.kernel.org, Jeff White <Jeff.White@....aero>,
        Russell King <linux@...linux.org.uk>,
        linux-kernel@...r.kernel.org, Rob Herring <robh+dt@...nel.org>,
        Sascha Hauer <kernel@...gutronix.de>,
        Vladimir Barinov <vladimir.barinov@...entembedded.com>,
        linux-arm-kernel@...ts.infradead.org,
        Chris Healy <Chris.Healy@....aero>
Subject: Re: [PATCH] ARM: dts: vf610-zii-dev-rev-b: add hi8435 device

On Thu, 25 May 2017 11:03:20 +0300
Nikita Yushchenko <nikita.yoush@...entembedded.com> wrote:

> >> "Crap origin" here is that in vast majority of cases, polarity is
> >> per-chip, not per-chip-use, knowledge. And proper location for per-chip
> >> knowledge is chip's driver.  Moving this knowledge to per-chip-use
> >> location in device trees only provides a source for errors, with little
> >> gain.
> >>
> >> Vladimir Barinov mentions possibility that signal can be inverted by
> >> board between gpio provider and chip's pin ...   but do we have at least
> >> one practical case of this?  And if we even do, it's quite uncommon, and
> >> something special should be required in device tree for these special
> >> cases and not for "normal" cases.  
> > 
> > I disagree.  Not for hi8435, but I have seen quite some board designs
> > invert GPIOs before getting them into board level components.  That's
> > why we should define those xxx-gpios properties on board level DTS,
> > where polarity can be chosen per board design.  
> 
> Even if such, still board specific knowledge is "is gpio as-is or
> inverted", but knowledge if chip expects signal to be active low or
> active high, remains chip-specific.
> 
> I'm thinking of proposing new flags in gpio binding, say
> GPIO_NATIVE_POLARITY / GPIO_INVERTED_POLARITY,  that could be used
> instead of GPIO_ACTIVE_HIGH / GPIO_ACTIVE_LOW, and leave knowledge about
> signal polarity to chip's driver, while still allow to describe
> inversion of needed.
Whilst I'm not certain on the precise approach (I'd be tempted by
heavy handed explicit representation of the inverting component) it
seems like this needs more thought.  I'm going to revert my
rather premature applying of the initial change for now.

Jonathan
> 
> Nikita

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ