linux-kernel - Re: [PATCH 3/4] mmc: sdhci-esdhc-imx: Allow all supported prescaler values

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Message-ID: <CAOMZO5BnTHce4Dn=ppvd5hV3ShrcTHZvv_DwkeUC9qtWrMv8Rw@mail.gmail.com>
Date:   Mon, 29 May 2017 08:14:11 -0300
From:   Fabio Estevam <festevam@...il.com>
To:     Benoît Thébaudeau <benoit@...stem.com>
Cc:     linux-kernel <linux-kernel@...r.kernel.org>,
        "linux-mmc@...r.kernel.org" <linux-mmc@...r.kernel.org>,
        Ulf Hansson <ulf.hansson@...aro.org>,
        Adrian Hunter <adrian.hunter@...el.com>,
        Fabio Estevam <fabio.estevam@....com>,
        Eric Bénard <eric@...rea.com>,
        Wolfram Sang <wsa@...-dreams.de>,
        Dong Aisheng <aisheng.dong@....com>
Subject: Re: [PATCH 3/4] mmc: sdhci-esdhc-imx: Allow all supported prescaler values

On Wed, May 3, 2017 at 7:05 AM, Benoît Thébaudeau <benoit@...stem.com> wrote:
> On i.MX, SYSCTL.SDCLKFS may always be set to 0 in order to make the SD
> clock frequency prescaler divide by 1 in SDR mode, even with the eSDHC.
> The previous minimum prescaler value of 2 in SDR mode with the eSDHC was
> a code remnant from PowerPC, which actually has this limitation on
> earlier revisions.
>
> In DDR mode, the prescaler can divide by up to 512.
>
> The maximum SD clock frequency in High Speed mode is 50 MHz. On i.MX25,
> this change makes it possible to get 48 MHz from the USB PLL
> (240 MHz / 5 / 1) instead of only 40 MHz from the USB PLL
> (240 MHz / 3 / 2) or 33.25 MHz from the AHB clock (133 MHz / 2 / 2).
>
> Signed-off-by: Benoît Thébaudeau <benoit@...stem.com>

Reviewed-by: Fabio Estevam <fabio.estevam@....com>