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Message-ID: <d70f8b0c-a17e-7cac-ff8e-227547ba0a4b@intel.com>
Date: Mon, 29 May 2017 11:02:00 +0300
From: Adrian Hunter <adrian.hunter@...el.com>
To: Benoît Thébaudeau <benoit@...stem.com>,
linux-kernel@...r.kernel.org, linux-mmc@...r.kernel.org
Cc: Ulf Hansson <ulf.hansson@...aro.org>,
Fabio Estevam <fabio.estevam@....com>,
joancarles <joancarles@...ngenieria.es>,
Eric Bénard <eric@...rea.com>,
Wolfram Sang <wsa@...-dreams.de>
Subject: Re: [PATCH 1/4] mmc: sdhci-esdhc: Add SDHCI_QUIRK_32BIT_DMA_ADDR
On 03/05/17 13:05, Benoît Thébaudeau wrote:
> The eSDHC can only DMA from 32-bit-aligned addresses.
>
> This fixes the following test cases of mmc_test:
> 11: Badly aligned write
> 12: Badly aligned read
> 13: Badly aligned multi-block write
> 14: Badly aligned multi-block read
>
> Signed-off-by: Benoît Thébaudeau <benoit@...stem.com>
I would expect to see Acks from other sdhci-esdhc users. Nevertheless for
sdhci:
Acked-by: Adrian Hunter <adrian.hunter@...el.com>
> ---
> drivers/mmc/host/sdhci-esdhc.h | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/mmc/host/sdhci-esdhc.h b/drivers/mmc/host/sdhci-esdhc.h
> index c4bbd74..e7893f2 100644
> --- a/drivers/mmc/host/sdhci-esdhc.h
> +++ b/drivers/mmc/host/sdhci-esdhc.h
> @@ -19,6 +19,7 @@
> */
>
> #define ESDHC_DEFAULT_QUIRKS (SDHCI_QUIRK_FORCE_BLK_SZ_2048 | \
> + SDHCI_QUIRK_32BIT_DMA_ADDR | \
> SDHCI_QUIRK_NO_BUSY_IRQ | \
> SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK | \
> SDHCI_QUIRK_PIO_NEEDS_DELAY | \
>
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