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Message-ID: <20170530161731.33fec50d@roar.ozlabs.ibm.com>
Date: Tue, 30 May 2017 16:17:31 +1000
From: Nicholas Piggin <npiggin@...il.com>
To: "Gautham R. Shenoy" <ego@...ux.vnet.ibm.com>
Cc: Michael Ellerman <mpe@...erman.id.au>,
Michael Neuling <mikey@...ling.org>,
Vaidyanathan Srinivasan <svaidy@...ux.vnet.ibm.com>,
Shilpasri G Bhat <shilpa.bhat@...ux.vnet.ibm.com>,
Akshay Adiga <akshay.adiga@...ux.vnet.ibm.com>,
Benjamin Herrenschmidt <benh@...nel.crashing.org>,
linuxppc-dev@...ts.ozlabs.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 3/6] powernv:idle: Restore LPCR on wakeup from deep-stop
On Tue, 16 May 2017 14:19:45 +0530
"Gautham R. Shenoy" <ego@...ux.vnet.ibm.com> wrote:
> From: "Gautham R. Shenoy" <ego@...ux.vnet.ibm.com>
>
> On wakeup from a deep stop state which is supposed to lose the
> hypervisor state, we don't restore the LPCR to the old value but set
> it to a "sane" value via cur_cpu_spec->cpu_restore().
>
> The problem is that the "sane" value doesn't include UPRT and the HR
> bits which are required to run correctly in Radix mode.
>
> Fix this on POWER9 onwards by restoring the LPCR value whatever it was
> before executing the stop instruction.
>
> Signed-off-by: Gautham R. Shenoy <ego@...ux.vnet.ibm.com>
Yes I think we need this. I have a plan to rework some of
that cpu_restore and early CPU init stuff, but for now we
need this.
Does the OCC restore LPCR properly then we just trash it
with ->cpu_restore(), or is it always junk?
Reviewed-by: Nicholas Piggin <npiggin@...il.com>
> ---
> arch/powerpc/kernel/idle_book3s.S | 13 ++++++++++---
> 1 file changed, 10 insertions(+), 3 deletions(-)
>
> diff --git a/arch/powerpc/kernel/idle_book3s.S b/arch/powerpc/kernel/idle_book3s.S
> index afd029f..6c9920d 100644
> --- a/arch/powerpc/kernel/idle_book3s.S
> +++ b/arch/powerpc/kernel/idle_book3s.S
> @@ -31,6 +31,7 @@
> * registers for winkle support.
> */
> #define _SDR1 GPR3
> +#define _PTCR GPR3
> #define _RPR GPR4
> #define _SPURR GPR5
> #define _PURR GPR6
> @@ -39,7 +40,7 @@
> #define _AMOR GPR9
> #define _WORT GPR10
> #define _WORC GPR11
> -#define _PTCR GPR12
> +#define _LPCR GPR12
>
> #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
>
> @@ -55,12 +56,14 @@ save_sprs_to_stack:
> * here since any thread in the core might wake up first
> */
> BEGIN_FTR_SECTION
> - mfspr r3,SPRN_PTCR
> - std r3,_PTCR(r1)
> /*
> * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
> * SDR1 here
> */
> + mfspr r3,SPRN_PTCR
> + std r3,_PTCR(r1)
> + mfspr r3,SPRN_LPCR
> + std r3,_LPCR(r1)
> FTR_SECTION_ELSE
> mfspr r3,SPRN_SDR1
> std r3,_SDR1(r1)
> @@ -813,6 +816,10 @@ no_segments:
> mtctr r12
> bctrl
>
> +BEGIN_FTR_SECTION
> + ld r4,_LPCR(r1)
> + mtspr SPRN_LPCR,r4
> +END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
> hypervisor_state_restored:
>
> mtspr SPRN_SRR1,r16
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