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Message-ID: <20170530165454.6ca24dbc@free-electrons.com>
Date: Tue, 30 May 2017 16:54:54 +0200
From: Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
To: Marc Zyngier <marc.zyngier@....com>
Cc: Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
Rob Herring <robh+dt@...nel.org>,
Ian Campbell <ijc+devicetree@...lion.org.uk>,
Pawel Moll <pawel.moll@....com>,
Mark Rutland <mark.rutland@....com>,
Kumar Gala <galak@...eaurora.org>,
Andrew Lunn <andrew@...n.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Gregory Clement <gregory.clement@...e-electrons.com>,
linux-arm-kernel@...ts.infradead.org,
Nadav Haklai <nadavh@...vell.com>,
Hanna Hawa <hannah@...vell.com>,
Yehuda Yitschak <yehuday@...vell.com>,
Antoine Tenart <antoine.tenart@...e-electrons.com>
Subject: Re: [PATCH 3/6] irqchip: irq-mvebu-gicp: new driver for Marvell
GICP
Hello,
On Tue, 30 May 2017 14:55:57 +0100, Marc Zyngier wrote:
> > + for (i = 0; i < GICP_INT_COUNT; i++)
> > + writel(i, regs + GICP_CLRSPI_NSR_OFFSET);
>
> What does this do on an edge interrupt?
I guess nothing. What the ICU does is:
* For level interrupts: when the interrupt wire is asserted, write to
SETNSR, when the interrupt wire is deasserted, write to CLRNSR
* For edge interrupts: only the interrupt assertion causes a write to
SETNSR.
> I bet this doesn't have any effect
Indeed. But do we care? Can an edge interrupt be left pending from the
firmware?
>, so you may want to use the irq_set_irqchip_state() API to clear a
> potential pending state instead (and you may want to wire it in the
> ICU driver itself as well).
I'm not sure how to use this irq_set_irqchip_state() API. I guess it
needs a virq that corresponds to the GIC SPI interrupt, and I'm not
sure how to get that.
Thomas
--
Thomas Petazzoni, CTO, Free Electrons
Embedded Linux and Kernel engineering
http://free-electrons.com
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