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Message-ID: <20170531070109.81569-3-songxiaowei@hisilicon.com>
Date: Wed, 31 May 2017 15:01:07 +0800
From: Xiaowei Song <songxiaowei@...ilicon.com>
To: <bhelgaas@...gle.com>, <kishon@...com>, <jingoohan1@...il.com>,
<arnd@...db.de>, <tn@...ihalf.com>, <keith.busch@...el.com>,
<niklas.cassel@...s.com>, <dhdang@....com>,
<liudongdong3@...wei.com>, <gabriele.paoloni@...wei.com>,
<robh+dt@...nel.org>, <mark.rutland@....com>,
<catalin.marinas@....com>, <will.deacon@....com>
CC: <chenyao11@...wei.com>, <puck.chen@...ilicon.com>,
<songxiaowei@...ilicon.com>, <guodong.xu@...aro.org>,
<wangbinghui@...ilicon.com>, <suzhuangluan@...ilicon.com>,
<linux-pci@...r.kernel.org>, <devicetree@...r.kernel.org>,
<linux-kernel@...r.kernel.org>
Subject: [PATCH v9 2/4] arm64: dts: hisi: add kirin pcie node
Add PCIe node for hi3660, and add binding documentation.
Cc: Guodong Xu <guodong.xu@...aro.org>
Signed-off-by: Xiaowei Song <songxiaowei@...ilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 31 +++++++++++++++++++++++++++++++
1 file changed, 31 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
index 3983086bd67b..e8feb2fb4d53 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi
@@ -156,5 +156,36 @@
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
+
+ pcie@...00000 {
+ compatible = "hisilicon,kirin960-pcie";
+ reg = <0x0 0xf4000000 0x0 0x1000>,
+ <0x0 0xff3fe000 0x0 0x1000>,
+ <0x0 0xf3f20000 0x0 0x40000>,
+ <0x0 0xF5000000 0x0 0x2000>;
+ reg-names = "dbi", "apb", "phy", "config";
+ bus-range = <0x0 0x1>;
+ #address-cells = <3>;
+ #size-cells = <2>;
+ device_type = "pci";
+ ranges = <0x02000000 0x0 0x00000000 0x0
+ 0xf6000000 0x0 0x2000000>;
+ num-lanes = <1>;
+ #interrupt-cells = <1>;
+ interrupt-map-mask = <0xf800 0 0 7>;
+ interrupt-map = <0x0 0 0 1 &gic 0 0 0 282 4>,
+ <0x0 0 0 2 &gic 0 0 0 283 4>,
+ <0x0 0 0 3 &gic 0 0 0 284 4>,
+ <0x0 0 0 4 &gic 0 0 0 285 4>;
+ clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
+ <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
+ <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
+ <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
+ clock-names = "pcie_phy_ref", "pcie_aux",
+ "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
+ reset-gpios = <&gpio11 1 0 >;
+ status = "ok";
+ };
};
};
--
2.11.GIT
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