lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20170531183846.GB31565@khazad-dum.debian.net>
Date:   Wed, 31 May 2017 15:38:47 -0300
From:   Henrique de Moraes Holschuh <hmh@....eng.br>
To:     Peter Zijlstra <peterz@...radead.org>
Cc:     tglx@...utronix.de, x86@...nel.org, linux-kernel@...r.kernel.org,
        kevin.b.stanton@...el.com
Subject: Re: [PATCH 0/3] x86: TSC_DEADLINE vs TSC_ADJUST and microcode
 revisions

On Wed, 31 May 2017, Peter Zijlstra wrote:
> These patches rely on the latest microcode data files from Intel [*]
> 
> Without this microcode loaded, we'll print a FW_BUG informing the user to
> update their microcode image and disable TSC_DEADLINE support.
> 
> This in turn allows us to remove the TSC_ADJUST workarounds which were required
> due to errata.

Thanks!

On a related note, maybe it would be possible to do something about
SKL150/SKX150/KBL095 as well?

Working around that errata requires disabling hyperthreads on Skylake
when microcode < 0xb9 (confirmed to fix the issue by users suffering
from SKL150), and for Kabylake, disable hyperthreading when microcode <
0x5d (personal best guess based on microcode release date -- someone
@intel might want to confirm it).

-- 
  Henrique Holschuh

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ