lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20170601082804.GE20170@codeaurora.org>
Date:   Thu, 1 Jun 2017 01:28:04 -0700
From:   Stephen Boyd <sboyd@...eaurora.org>
To:     Yuantian Tang <andy.tang@....com>
Cc:     mturquette@...libre.com, robh+dt@...nel.org, mark.rutland@....com,
        linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        Scott Wood <oss@...error.net>
Subject: Re: [PATCH 2/2 v2] clk: qoriq: Separate root input clock for core
 PLLs on ls1012a

On 03/20, Yuantian Tang wrote:
> From: Scott Wood <oss@...error.net>
> 
> ls1012a has separate input root clocks for core PLLs versus the
> platform PLL, with the latter described as sysclk in the hw docs.
> If a second input clock, named "coreclk", is present, this clock will be
> used for the core PLLs.
> 
> Signed-off-by: Scott Wood <oss@...error.net>
> Signed-off-by: Tang Yuantian <andy.tang@....com>
> Acked-by: Rob Herring <robh@...nel.org>
> ---

Applied to clk-next

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,
a Linux Foundation Collaborative Project

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ