| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <7b92aabfb7309eb0b138c149cc3fc61e8f64cd61.1496413293.git-series.gregory.clement@free-electrons.com>
Date: Fri, 2 Jun 2017 16:23:16 +0200
From: Gregory CLEMENT <gregory.clement@...e-electrons.com>
To: Linus Walleij <linus.walleij@...aro.org>,
linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org
Cc: Jason Cooper <jason@...edaemon.net>, Andrew Lunn <andrew@...n.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Gregory CLEMENT <gregory.clement@...e-electrons.com>,
Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>,
linux-arm-kernel@...ts.infradead.org,
Rob Herring <robh+dt@...nel.org>, devicetree@...r.kernel.org,
Russell King <rmk+kernel@...linux.org.uk>,
Nadav Haklai <nadavh@...vell.com>,
Kostya Porotchkin <kostap@...vell.com>,
Neta Zur Hershkovits <neta@...vell.com>,
Marcin Wojtas <mw@...ihalf.com>,
Omri Itach <omrii@...vell.com>,
Shadi Ammouri <shadi@...vell.com>
Subject: [PATCH v2 09/11] gpio: dt-bindings: Add documentation for gpio controllers on Armada 7K/8K
Document the device tree binding for the gpio controllers found on the
Marvell Armada 7K and Armada 8K SoCs.
Signed-off-by: Gregory CLEMENT <gregory.clement@...e-electrons.com>
---
Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt | 20 ++++++++++++++++++++
Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt | 24 +++++++++++++++++++++++-
Documentation/devicetree/bindings/gpio/gpio-mvebu.txt | 24 +++++++++++++++++-------
3 files changed, 60 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
index 4228d158fb31..0b887440e08a 100644
--- a/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
@@ -64,6 +64,17 @@ mpp17 17 gpio
mpp18 18 gpio
mpp19 19 gpio, uart0(rxd), sdio(pw_off)
+GPIO:
+-----
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-8k-gpio"
+
+- offset: offset address inside the syscon block
+
Example:
ap_syscon: system-controller@...000 {
compatible = "syscon", "simple-mfd";
@@ -77,4 +88,13 @@ ap_syscon: system-controller@...000 {
ap_pinctrl: pinctrl {
compatible = "marvell,ap806-pinctrl";
};
+
+ ap_gpio: gpio {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x1040>;
+ ngpios = <19>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&ap_pinctrl 0 0 19>;
+ };
};
diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
index 733beac7724e..655c114ef584 100644
--- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
@@ -149,6 +149,18 @@ mpp60 60 gpio, mss_gpio6, ptp(pulse), tdm(dtx), au(i2smclk), spi0(csn1), uart0(r
mpp61 61 gpio, mss_gpio5, ptp(clk), tdm(pclk), au(i2sextclk), spi0(csn2), uart0(txd), uart2(txd), sata1(present_act), ge(mdio), sdio(d3)
mpp62 62 gpio, mss_gpio4, synce1(clk), ptp(pclk_out), sata1(present_act), spi0(csn3), uart0(rxd), uart2(rxd), sata0(present_act), ge(mdc)
+GPIO:
+-----
+
+For common binding part and usage, refer to
+Documentation/devicetree/bindings/gpio/gpio-mvebu.txt.
+
+Required properties:
+
+- compatible: "marvell,armada-8k-gpio"
+
+- offset: offset address inside the syscon block
+
Example:
cpm_syscon0: system-controller@...000 {
@@ -163,5 +175,15 @@ cpm_syscon0: system-controller@...000 {
cpm_pinctrl: pinctrl {
compatible = "marvell,armada-8k-cpm-pinctrl";
};
-};
+ cpm_gpio1: gpio@100 {
+ compatible = "marvell,armada-8k-gpio";
+ offset = <0x100>;
+ ngpios = <32>;
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&cpm_pinctrl 0 0 32>;
+ status = "disabled";
+ };
+
+};
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
index 42c3bb2d53e8..2c5304ff467c 100644
--- a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -2,17 +2,27 @@
Required properties:
-- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
- or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
- Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
- 370. "marvell,mv78200-gpio" should be used for the Discovery
- MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
- SoCs (MV78230, MV78260, MV78460).
+- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio",
+ "marvell,armadaxp-gpio" or "marvell,armada-8k-gpio".
+
+ "marvell,orion-gpio" should be used for Orion, Kirkwood, Dove,
+ Discovery (except MV78200) and Armada 370. "marvell,mv78200-gpio"
+ should be used for the Discovery MV78200.
+
+ "marvel,armadaxp-gpio" should be used for all Armada XP SoCs
+ (MV78230, MV78260, MV78460).
+
+ "marvell,armada-8k-gpio" should be used for the Armada 7K and 8K
+ SoCs (either from AP or CP), see
+ Documentation/devicetree/bindings/arm/marvell/cp110-system-controller0.txt
+ and
+ Documentation/devicetree/bindings/arm/marvell/ap806-system-controller.txt
+ for specific details about the offset property.
- reg: Address and length of the register set for the device. Only one
entry is expected, except for the "marvell,armadaxp-gpio" variant
for which two entries are expected: one for the general registers,
- one for the per-cpu registers.
+ one for the per-cpu registers. Not used for marvell,armada-8k-gpio.
- interrupts: The list of interrupts that are used for all the pins
managed by this GPIO bank. There can be more than one interrupt
--
git-series 0.9.1
Powered by blists - more mailing lists