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Date: Sat, 3 Jun 2017 22:44:27 +0800 From: Chen-Yu Tsai <wens@...e.org> To: Maxime Ripard <maxime.ripard@...e-electrons.com>, Linus Walleij <linus.walleij@...aro.org>, Rob Herring <robh+dt@...nel.org>, Mark Rutland <mark.rutland@....com> Cc: Chen-Yu Tsai <wens@...e.org>, linux-arm-kernel@...ts.infradead.org, linux-gpio@...r.kernel.org, linux-kernel@...r.kernel.org, devicetree@...r.kernel.org, linux-sunxi@...glegroups.com Subject: [PATCH 3/3] ARM: sun8i: a83t: Add device node for R_PIO The A83T has 1 pingroup with 13 pins belonging to the R_PIO or special pin controller. Signed-off-by: Chen-Yu Tsai <wens@...e.org> --- arch/arm/boot/dts/sun8i-a83t.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi index 49aeb56970ba..bf63e3b77572 100644 --- a/arch/arm/boot/dts/sun8i-a83t.dtsi +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi @@ -44,6 +44,8 @@ #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/sun8i-r-ccu.h> + / { interrupt-parent = <&gic>; #address-cells = <1>; @@ -280,5 +282,18 @@ #clock-cells = <1>; #reset-cells = <1>; }; + + r_pio: pinctrl@...2c00 { + compatible = "allwinner,sun8i-a83t-r-pinctrl"; + reg = <0x01f02c00 0x400>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>, + <&osc16Md512>; + clock-names = "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells = <3>; + interrupt-controller; + #interrupt-cells = <3>; + }; }; }; -- 2.11.0
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