linux-kernel - Re: [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks

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Message-ID: <13a14a47-1609-4b44-1bb1-6f58c9cda914@hauke-m.de>
Date:   Sat, 3 Jun 2017 17:55:04 +0200
From:   Hauke Mehrtens <hauke@...ke-m.de>
To:     Martin Schiller <ms@....tdt.de>, linux-mips@...ux-mips.org,
        linux-kernel@...r.kernel.org
Cc:     john@...ozen.org, ralf@...ux-mips.org, arnd@...db.de, nbd@....name
Subject: Re: [PATCH] MIPS: Lantiq: Fix ASC0/ASC1 clocks

On 05/30/2017 06:34 AM, Martin Schiller wrote:
> ASC1 is available on every Lantiq SoC (also AmazonSE) and should be
> enabled like the other generic xway clocks instead of ASC0, which is
> only available for AR9 and Danube.

This is correct.

> Signed-off-by: Martin Schiller <ms@....tdt.de>

Acked-by: Hauke Mehrtens <hauke@...ke-m.de>

> ---
>  arch/mips/lantiq/xway/sysctrl.c | 3 +--
>  1 file changed, 1 insertion(+), 2 deletions(-)
> 
> diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
> index 95bec46..cd6dbea 100644
> --- a/arch/mips/lantiq/xway/sysctrl.c
> +++ b/arch/mips/lantiq/xway/sysctrl.c
> @@ -484,9 +484,9 @@ void __init ltq_soc_init(void)
>  
>  	/* add our generic xway clocks */
>  	clkdev_add_pmu("10000000.fpi", NULL, 0, 0, PMU_FPI);
> -	clkdev_add_pmu("1e100400.serial", NULL, 0, 0, PMU_ASC0);
>  	clkdev_add_pmu("1e100a00.gptu", NULL, 1, 0, PMU_GPT);
>  	clkdev_add_pmu("1e100bb0.stp", NULL, 1, 0, PMU_STP);
> +	clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
>  	clkdev_add_pmu("1e104100.dma", NULL, 1, 0, PMU_DMA);
>  	clkdev_add_pmu("1e100800.spi", NULL, 1, 0, PMU_SPI);
>  	clkdev_add_pmu("1e105300.ebu", NULL, 0, 0, PMU_EBU);
> @@ -501,7 +501,6 @@ void __init ltq_soc_init(void)
>  	}
>  
>  	if (!of_machine_is_compatible("lantiq,ase")) {
> -		clkdev_add_pmu("1e100c00.serial", NULL, 0, 0, PMU_ASC1);
>  		clkdev_add_pci();
>  	}
>  
>