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Message-ID: <CAHp75VedMd9+-Z+1m49AqBOzHj3qPxw08B4BKOpyKvNntTU_bg@mail.gmail.com>
Date:   Mon, 5 Jun 2017 18:20:50 +0300
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     Mika Westerberg <mika.westerberg@...ux.intel.com>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Heikki Krogerus <heikki.krogerus@...ux.intel.com>,
        "linux-gpio@...r.kernel.org" <linux-gpio@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 0/3] pinctrl: Add support for Intel Cannon Lake PCH

On Mon, Jun 5, 2017 at 3:56 PM, Mika Westerberg
<mika.westerberg@...ux.intel.com> wrote:
> Hi,
>
> This series adds support for the pinctrl and GPIO hardware found on the
> next generation Intel Cannon Lake CPUs. We also update the Intel core
> pinctrl driver with a concept of hardware pad groups that are needed by the
> new driver and make it possible to specify mode per pin instead of the
> whole group.
>

One comment to be considered, otherwise

Reviewed-by: Andy Shevchenko <andy.shevchenko@...il.com>

> Mika Westerberg (3):
>   pinctrl: intel: Add support for variable size pad groups
>   pinctrl: intel: Make it possible to specify mode per pin in a group
>   pinctrl: intel: Add Intel Cannon Lake PCH pin controller support
>
>  drivers/pinctrl/intel/Kconfig                |   8 +
>  drivers/pinctrl/intel/Makefile               |   1 +
>  drivers/pinctrl/intel/pinctrl-cannonlake.c   | 442 +++++++++++++++++++++++++++
>  drivers/pinctrl/intel/pinctrl-intel.c        | 195 ++++++++----
>  drivers/pinctrl/intel/pinctrl-intel.h        |  64 +++-
>  drivers/pinctrl/intel/pinctrl-sunrisepoint.c |   1 +
>  6 files changed, 647 insertions(+), 64 deletions(-)
>  create mode 100644 drivers/pinctrl/intel/pinctrl-cannonlake.c
>
> --
> 2.11.0
>



-- 
With Best Regards,
Andy Shevchenko

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