linux-kernel - Re: [PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for second level IRQ chips

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 6 Jun 2017 12:29:03 +0300
From:   Heikki Krogerus <heikki.krogerus@...ux.intel.com>
To:     sathyanarayanan.kuppuswamy@...ux.intel.com
Cc:     gnurou@...il.com, gregkh@...uxfoundation.org,
        linus.walleij@...aro.org, edubezval@...il.com,
        dvhart@...radead.org, rui.zhang@...el.com, lee.jones@...aro.org,
        andy@...radead.org, platform-driver-x86@...r.kernel.org,
        linux-gpio@...r.kernel.org, linux-usb@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-pm@...r.kernel.org,
        sathyaosid@...il.com
Subject: Re: [PATCH v6 5/6] mfd: intel_soc_pmic_bxtwc: Use chained IRQs for
 second level IRQ chips

On Mon, Jun 05, 2017 at 12:08:05PM -0700, sathyanarayanan.kuppuswamy@...ux.intel.com wrote:
> From: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
> 
> Whishkey cove PMIC has support to mask/unmask interrupts at two levels.
> At first level we can mask/unmask interrupt domains like TMU, GPIO, ADC,
> CHGR, BCU THERMAL and PWRBTN and at second level, it provides facility
> to mask/unmask individual interrupts belong each of this domain. For
> example, in case of TMU, at first level we have TMU interrupt domain,
> and at second level we have two interrupts, wake alarm, system alarm that
> belong to the TMU interrupt domain.
> 
> Currently, in this driver all first level IRQs are registered as part of
> IRQ chip(bxtwc_regmap_irq_chip). By default, after you register the IRQ
> chip from your driver, all IRQs in that chip will masked and can only be
> enabled if that IRQ is requested using request_irq() call. This is the
> default Linux IRQ behavior model. And whenever a dependent device that
> belongs to PMIC requests only the second level IRQ and not explicitly
> unmask the first level IRQ, then in essence the second level IRQ will
> still be disabled. For example, if TMU device driver request wake_alarm
> IRQ and not explicitly unmask TMU level 1 IRQ then according to the default
> Linux IRQ model,  wake_alarm IRQ will still be disabled. So the proper
> solution to fix this issue is to use the chained IRQ chip concept. We
> should chain all the second level chip IRQs to the corresponding first
> level IRQ. To do this, we need to create separate IRQ chips for every
> group of second level IRQs.
> 
> In case of TMU, when adding second level IRQ chip, instead of using PMIC
> IRQ we should use the corresponding first level IRQ. So the following
> code will change from
> 
> ret = regmap_add_irq_chip(pmic->regmap, pmic->irq, ...)
> 
> to,
> 
> virq = regmap_irq_get_virq(&pmic->irq_chip_data, BXTWC_TMU_LVL1_IRQ);
> 
> ret = regmap_add_irq_chip(pmic->regmap, virq, ...)
> 
> In case of Whiskey Cove Type-C driver, Since USBC IRQ is moved under
> charger level2 IRQ chip. We should use charger IRQ chip(irq_chip_data_chgr)
> to get the USBC virtual IRQ number.
> 
> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@...ux.intel.com>
> Acked-for-MFD-by: Lee Jones <lee.jones@...aro.org>

For the typec_wcove.c part:

Revieved-by: Heikki Krogerus <heikki.krogerus@...ux.intel.com>


Thanks,

-- 
heikki