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Date: Tue, 6 Jun 2017 13:33:41 -0300
From: Fabio Estevam <festevam@...il.com>
To: Stefan Agner <stefan@...er.ch>
Cc: Shawn Guo <shawnguo@...nel.org>,
Sascha Hauer <kernel@...gutronix.de>,
Stephen Boyd <sboyd@...eaurora.org>,
Dong Aisheng <aisheng.dong@....com>,
David Woodhouse <dwmw2@...radead.org>,
Brian Norris <computersforpeace@...il.com>,
Boris Brezillon <boris.brezillon@...e-electrons.com>,
Marek Vasut <marek.vasut@...il.com>,
Richard Weinberger <richard@....at>,
"robh+dt@...nel.org" <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>, han.xu@....com,
Fabio Estevam <fabio.estevam@...escale.com>,
Lothar Waßmann <LW@...o-electronics.de>,
"linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
"devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
"linux-arm-kernel@...ts.infradead.org"
<linux-arm-kernel@...ts.infradead.org>, linux-clk@...r.kernel.org,
linux-kernel <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v5 1/3] clk: imx7d: create clocks behind rawnand clock gate
On Tue, Jun 6, 2017 at 3:30 AM, Stefan Agner <stefan@...er.ch> wrote:
> The rawnand clock gate gates two clocks, NAND_USDHC_BUS_CLK_ROOT
> and NAND_CLK_ROOT. However, the gate has been in the chain of the
> latter only. This does not allow to use the NAND_USDHC_BUS_CLK_ROOT
> only, e.g. as required by APBH-Bridge-DMA.
>
> Add new clocks which represent the clock after the gate, and use a
> shared clock gate to correctly model the hardware.
>
> Signed-off-by: Stefan Agner <stefan@...er.ch>
Tested-by: Fabio Estevam <fabio.estevam@....com>
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