linux-kernel - Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding for the Marvell GICP

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 7 Jun 2017 17:24:20 -0500
From:   Rob Herring <robh@...nel.org>
To:     Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
Cc:     Thomas Gleixner <tglx@...utronix.de>,
        Jason Cooper <jason@...edaemon.net>,
        Marc Zyngier <marc.zyngier@....com>,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        Ian Campbell <ijc+devicetree@...lion.org.uk>,
        Pawel Moll <pawel.moll@....com>,
        Mark Rutland <mark.rutland@....com>,
        Kumar Gala <galak@...eaurora.org>,
        Andrew Lunn <andrew@...n.ch>,
        Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
        Gregory Clement <gregory.clement@...e-electrons.com>,
        Nadav Haklai <nadavh@...vell.com>,
        Hanna Hawa <hannah@...vell.com>,
        Yehuda Yitschak <yehuday@...vell.com>,
        Antoine Tenart <antoine.tenart@...e-electrons.com>,
        linux-arm-kernel@...ts.infradead.org
Subject: Re: [PATCH v2 1/6] dt-bindings: interrupt-controller: add DT binding
 for the Marvell GICP

On Fri, Jun 02, 2017 at 12:06:52PM +0200, Thomas Petazzoni wrote:
> This commit adds the Device Tree binding documentation for the Marvell
> GICP, an extension to the GIC that allows to trigger GIC SPI interrupts
> using memory transactions. It is used by the ICU unit in the Marvell
> CP110 block to turn wired interrupts inside the CP into SPI interrupts
> at the GIC level in the AP.

Sounds like an MSI block?

> Signed-off-by: Thomas Petazzoni <thomas.petazzoni@...e-electrons.com>
> ---
>  .../bindings/interrupt-controller/marvell,gicp.txt | 24 ++++++++++++++++++++++
>  1 file changed, 24 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
> new file mode 100644
> index 0000000..3fc36963
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,gicp.txt
> @@ -0,0 +1,24 @@
> +Marvell GICP Controller
> +-----------------------
> +
> +GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
> +interrupts by doing a memory transaction. It is used by the ICU
> +located in the Marvell CP110 to turn wired interrupts inside the CP
> +into GIC SPI interrupts.
> +
> +Required properties:
> +
> +- compatible: Must be "marvell,ap806-gicp"
> +
> +- reg: Must be the address and size of the GICP SPI registers
> +
> +- marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
> +  for this GICP

These are base+size?

> +
> +Example:
> +
> +gicp_spi: gicp-spi@...040 {
> +	compatible = "marvell,ap806-gicp";
> +	reg = <0x3f0040 0x10>;
> +	marvell,spi-ranges = <64 64>, <288 64>;
> +};
> -- 
> 2.7.4
>