linux-kernel - Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an exception

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Message-ID: <67715c5d-30f2-815e-87ab-7fb4e8205a90@synopsys.com>
Date:   Thu, 8 Jun 2017 12:00:38 -0700
From:   Vineet Gupta <Vineet.Gupta1@...opsys.com>
To:     Noam Camus <noamca@...lanox.com>
CC:     "linux-snps-arc@...ts.infradead.org" 
        <linux-snps-arc@...ts.infradead.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Elad Kanfi <eladkan@...lanox.com>
Subject: Re: [PATCH v2 11/11] ARC: [plat-eznps] Handle memory error as an
 exception


On 06/08/2017 11:23 AM, Noam Camus wrote:
>
>
> *> From:* Vineet Gupta <Vineet.Gupta1@...opsys.com>
> *> Sent:* Thursday, June 8, 2017 7:38 PM
>
> >>
> >> With simulator we just turn this configuration on, so we redirect the Legacy
> >> Synopsys L2 ISR from nSIM into machine check.
> >> This way we end up just like with silicon 😊
>
> >This doesn't make sense :-)
> >In simulation (where L2 interrupt is asserted), you need to handle it as such -
> >say reading out the banked regs for L2 interrupt. What you are doing here is
> >handling it like an exception which won't work . I really don't see the point of
> >this "alignment" - hardware and simulation are different. simulation semantics are
> >already supported by generic ARC code. And for silicon case, the existing vector
> >woudl MachineCheck would work for both K and U. So I'm not sure what we are trying
> >to achieve here !
> With EZsim we try to simulate NPS400 CTOP core and not ARC core, and as such we 
> strive to have similar echo system for both silicon and its simulator.

Right, but if you are using nSIM which generates L2 interrupt for user mode error 
- then it is already different from silicon and needs to handled as such.

> If we could, we would alter nSIM to behave just like our silicon.
> So in current situation where we lack doing so we suffice in single pretty small 
> adjustment in OS (platform specific code).

You are saying contradicting things here. Above u want EZSim to simulate CTOP 
(i.e. generate machinechk for U errors) but here you claim u use nSIM which will 
generates L2 intr.

So I'm still grossly confused.

What does EZSim (based on nSIM) do when bus error is triggered from User mode - 
does it raise (A) L2 interrupt or (B) MachineCheck ?

If it is (A) the the existing common code in ARC will work - mem_service() -> 
do_memory_error() -> panic()
if it is (B), again the common machinecheck handler will be called and will panic.

I don't see the need to mix both (A) and (B) i.e. use mem_service() which is a L2 
interrupt, but then handle it in MachieChekc which is for exceptions ? How is that 
supposed to work !

-Vineet